A pipeline time-to-digital converter with a programmable time amplifier

This paper presents a pipeline time-to-digital converter (TDC) using a programmable time amplifier (TA). The TA adds time intervals that contain quantization errors in different stages of the first conversion step to achieve time amplification. Therefore, the TA has advantages of programmability, good linearity and wide input range. The TDC is designed in a 65nm CMOS technology. A time resolution up to 5ps at 230MHz is achieved. The total power consumption is 3mW under a 1V supply.

[1]  Pavan Kumar Hanumolu,et al.  A Digital PLL With a Stochastic Time-to-Digital Converter , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[2]  Paul Leroux,et al.  1-1-1 MASH $\Delta \Sigma$ Time-to-Digital Converters With 6 ps Resolution and Third-Order Noise-Shaping , 2012, IEEE Journal of Solid-State Circuits.

[3]  P. Dudek,et al.  A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line , 2000, IEEE Journal of Solid-State Circuits.

[4]  Rong Wang,et al.  A 2.4-GHz all-digital phase-locked loop with a pipeline-ΔΣ time-to-digital converter , 2017, IEICE Electron. Express.

[5]  Jianhui Wu,et al.  A 2.4-GHz All-Digital PLL With a 1-ps Resolution 0.9-mW Edge-Interchanging-Based Stochastic TDC , 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.

[6]  Robert B. Staszewski,et al.  Spur-Free Multirate All-Digital PLL for Mobile Phones in 65 nm CMOS , 2011, IEEE Journal of Solid-State Circuits.

[7]  K. Karadamoglou,et al.  An 11-bit high-resolution and adjustable-range CMOS time-to-digital converter for space science instruments , 2004, IEEE Journal of Solid-State Circuits.

[8]  Jae-Yoon Sim,et al.  A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 $\mu$ m CMOS , 2010, IEEE Journal of Solid-State Circuits.

[9]  E. Charbon,et al.  A 128-Channel, 8.9-ps LSB, Column-Parallel Two-Stage TDC Based on Time Difference Amplification for Time-Resolved Imaging , 2012, IEEE Transactions on Nuclear Science.

[10]  Dongming Zhou,et al.  An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA , 2018, IEEE Transactions on Instrumentation and Measurement.

[11]  A.A. Abidi,et al.  A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue , 2008, IEEE Journal of Solid-State Circuits.