Low-power, high-speed programmable logic array

Programmable logic arrays disclosed herein include end array and the OR array. And-array, and the synchronization is operated with a clock signal, in response to the input signal to generate a logical product signal. The OR array, and at least one signal line; A plurality of transistors operating in coupled to the signal line, the logical product in response to the portion of the signal; And as the above is coupled to at least one signal line, the enable clock signal comprises an enable circuit for synchronizing the operation of any one of said logic product signal.