A data processing apparatus includes a microprocessor which processes data and outputs m bits of data simultaneously and a semiconductor chip module. The module has a plurality of memory chips having data width of n bits data formed on each side of a substrate. The apparatus further includes data lines connected to the microprocessor and the memory chips for slicing m bit data into n bit data and providing the sliced n bit data to each memory chip. The data of a data processing apparatus is transmitted by the microprocessor and the memory chips. The microprocessor outputs an address signal to the memory chips. One group of the memory chips outputs data upper n bits to the microprocessor in parallel based on the address signal. The other group of the memory chips outputs data of lower (m-n) bits to the microprocessor in parallel based on the address signal.