Statistical modeling for computer-aided design of analog MOS integrated circuits

As MOS devices are scaled to meet increasingly demanding circuit specifications, process variations have a greater effect on the reliability of circuit performance. This is especially true for analog integrated circuits, where both inter-die and intra-die process variations have a significant effect on circuit operation. This dissertation describes a general, parameter-level statistical model, called SMOS (Statistical MOS), capable of generating statistically significant model decks from intra- and inter-die parameter statistics. Calculated model decks preserve the inherent correlations between model parameters while accounting for the dependence of parameter variance on device area, bias, and circuit layout. A procedure to tune the statistical model to a given fabrication process is detailed and applied to two test chips fabricated from different processes. Experimental and simulation results for two analog sub-circuits are compared to verify the statistical modeling algorithms. The MOS statistical model has been incorporated into two existing circuit simulators, SPICE and APLAC. In these CAD environments, the statistical model provides the analog circuit designer with a method to determine the effect of both circuit layout and device sizing on circuit output variance. Statistical analysis and simulation of two basic analog sub-circuits, the current mirror and the source-coupled pair, as well as a basic Miller-compensated operational amplifier are presented.