A 1036-F2/Bit High Reliability Temperature Compensated Cross-Coupled Comparator-Based PUF

In this article, a compact physical unclonable function (PUF) based on cross-coupled comparator is presented. Featuring a positive feedback response generation mechanism, the mismatch in analog signals between the cross-coupled transistor pair is quickly amplified to prevent its polarity from flipping by the temporal noise. The rapid enlargement of noise margin by the sense amplifier also contributes to stabilizing the response against supply voltage variations. To improve its temperature stability, the counteracting effect of complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) drives are considered in sizing the bit cell transistors. The proposed design is fabricated in a standard 65-nm CMOS process. The bit cell occupies an area of only $4.38~\mu \text {m}^{2}$ (i.e., $1036~F^{2}$ ), and the overall PUF chip consumes 2.98 pJ/bit at the throughput of 8 Mb/s, of which only 1.61 pJ/bit is due to the PUF’s core. With the uniqueness measured to be 49.53%, the unpredictability of the fabricated PUF chips is validated by autocorrelation function and NIST randomness tests. Compared with the state-of-the-art implementations, the proposed PUF has the lowest native response instability of 1.46% with 500 repeated PUF readouts at 27 °C and 1.2 V. By varying the operating temperature from −50 °C to 150 °C in a step size of 10 °C and the supply voltage from 1.0 to 1.4 V in a step size of 0.1 V simultaneously, the average reliability of the proposed PUF obtained from the 2-D plot of all operating conditions is found to be 96.87% without correction and 99.31% with spatial majority voting (SMV).

[1]  Yuan Cao,et al.  ACRO-PUF: A Low-power, Reliable and Aging-Resilient Current Starved Inverter-Based Ring Oscillator Physical Unclonable Function , 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

[2]  Massimo Alioto,et al.  Fully Synthesizable PUF Featuring Hysteresis and Temperature Compensation for 3.2% Native BER and 1.02 fJ/b in 40 nm , 2018, IEEE Journal of Solid-State Circuits.

[3]  Sudhir Satpathy,et al.  A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS , 2017, IEEE Journal of Solid-State Circuits.

[4]  Aijiao Cui,et al.  A New Pay-Per-Use Scheme for the Protection of FPGA IP , 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

[5]  Debdeep Mukhopadhyay,et al.  A Multiplexer-Based Arbiter PUF Composition with Enhanced Reliability and Security , 2018, IEEE Transactions on Computers.

[6]  Elaine B. Barker,et al.  A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications , 2000 .

[7]  Sergei Skorobogatov,et al.  Reverse Engineering Flash EEPROM Memories Using Scanning Electron Microscopy , 2016, CARDIS.

[8]  Wayne P. Burleson,et al.  On design of a highly secure PUF based on non-linear current mirrors , 2014, 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

[9]  Daniel E. Holcomb,et al.  Improving reliability of weak PUFs via circuit techniques to enhance mismatch , 2017, 2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

[10]  Jeyavijayan Rajendran,et al.  Keynote: A Disquisition on Logic Locking , 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Chip-Hong Chang,et al.  A New PUF Based Lock and Key Solution for Secure In-Field Testing of Cryptographic Chips , 2019, IEEE Transactions on Emerging Topics in Computing.

[12]  David Blaauw,et al.  8.3 A 553F2 2-transistor amplifier-based Physically Unclonable Function (PUF) with 1.67% native instability , 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

[13]  Yoonmyung Lee,et al.  A 445F2 leakage-based physically unclonable Function with Lossless Stabilization Through Remapping for IoT Security , 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

[14]  Yongki Lee,et al.  8.7 Physically unclonable function for secure key generation with a key error rate of 2E-38 in 45nm smart-card chips , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

[15]  Ulrich Rührmair,et al.  The Bistable Ring PUF: A new architecture for strong Physical Unclonable Functions , 2011, 2011 IEEE International Symposium on Hardware-Oriented Security and Trust.

[16]  Ingrid Verbauwhede,et al.  Machine learning attacks on 65nm Arbiter PUFs: Accurate modeling poses strict bounds on usability , 2012, 2012 IEEE International Workshop on Information Forensics and Security (WIFS).

[17]  Chuang Bai,et al.  A Reliable Strong PUF Based on Switched-Capacitor Circuit , 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[18]  Ying Su,et al.  A Digital 1.6 pJ/bit Chip Identification Circuit Using Process Variations , 2008, IEEE Journal of Solid-State Circuits.

[19]  Himanshu Kaul,et al.  16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[20]  Srinivas Devadas,et al.  Physical Unclonable Functions and Applications: A Tutorial , 2014, Proceedings of the IEEE.

[21]  Máire O'Neill,et al.  A machine learning attack resistant multi-PUF design on FPGA , 2018, 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC).

[22]  Jean-Pierre Seifert,et al.  Breaking and entering through the silicon , 2013, CCS.

[23]  Yuan Cao,et al.  A Low Power Diode-Clamped Inverter-Based Strong Physical Unclonable Function for Robust and Lightweight Authentication , 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

[24]  Farinaz Koushanfar,et al.  Active Hardware Metering for Intellectual Property Protection and Security , 2007, USENIX Security Symposium.

[25]  Arindam Basu,et al.  Current Mirror Array: A Novel Circuit Topology for Combining Physical Unclonable Function and Machine Learning , 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

[26]  Chip-Hong Chang,et al.  A Current Comparator Based Physical Unclonable Function with High Reliability and Energy Efficiency , 2018, 2018 IEEE 23rd International Conference on Digital Signal Processing (DSP).

[27]  Himanshu Kaul,et al.  2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors , 2012, IEEE Journal of Solid-State Circuits.

[28]  Massimo Alioto,et al.  14.3 15fJ/b static physically unclonable functions for secure chip identification with <2% native bit instability and 140× Inter/Intra PUF hamming distance separation in 65nm , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[29]  Mingoo Seok,et al.  Ultra-Compact and Robust Physically Unclonable Function Based on Voltage-Compensated Proportional-to-Absolute-Temperature Voltage Generators , 2016, IEEE Journal of Solid-State Circuits.

[30]  Daniel E. Holcomb,et al.  Initial SRAM State as a Fingerprint and Source of True Random Numbers for RFID Tags , 2007 .

[31]  Nahid Farhady Ghalaty,et al.  Differential Fault Intensity Analysis , 2014, 2014 Workshop on Fault Diagnosis and Tolerance in Cryptography.

[32]  Marten van Dijk,et al.  A technique to build a secret key in integrated circuits for identification and authentication applications , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

[33]  Chip-Hong Chang,et al.  A Retrospective and a Look Forward: Fifteen Years of Physical Unclonable Function Advancement , 2017, IEEE Circuits and Systems Magazine.