Real-time 25-Gb/s EPON OLT MAC/PHY with a Single FPGA for 100-Gb/s Access Networks

We implement an efficient, asymmetric 25-Gb/s Ethernet PON (EPON) OLT MAC/PHY that can support a rate of 25.78125-Gb/s in the downstream direction and 10.3125-Gb/s in the upstream direction, based on a single FPGA. We design based on the IEEE 802.3av 10G-EPON standard, and it includes a 25-Gb/s PCS/PMA and burst-mode 10-Gb/s PCS/PMA. In this paper, we demonstrate that the proposed the 25-Gb/s EPON OLT MAC/PHY can guarantee error-free packet service during a 72-h run time, and provide a packet throughput of 24-Gb/s and 9.6-Gb/s in downstream and upstream paths through a back-to-back link configuration.