Intrusive FPGA-in-the-loop debugging using a rule-based inference system

Abstract This paper presents an intrusive FPGA-in-the-loop (FIL) debugging methodology by using a rule-based inference system. In this methodology, a cycle-accurate lossless debugging system with unlimited trace window can be used to carry out debugging of an embedded design using FPGA-in-the-loop. Moreover, the approach can perform a runtime correspondence analysis between the HDL debugging data and a golden reference generated through a high level model, or through a behavioral, post-synthesis or post-implementation simulation results to speed up the debugging process. Furthermore, in the absence of a golden reference, the methodology can analyze the received debugging data and generate a golden reference on its own through pattern extraction from the received debugging data to speed up the process.

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