Ultra thin-wafer technology for a new 600 V-NPT-IGBT

In this paper the method of manufacturing 100 /spl mu/m thin IGBT wafers is described. The key topic of new deposition processes reducing the bow of very thin wafers is discussed as well as improvements in equipment and wafer handling. These measurements are the basis to realize for the first time 600 V Non-Punch-Through IGBTs with their advantages of cost effective silicon material and a very good trade off relationship between on state voltage and turn off losses. At a similar on state voltage of about 2 V the turn off energy can be halved compared to a state of the art epi IGBT.

[1]  G. Tam,et al.  Analysis of direct wafer bond IGBTs with heavily doped N+ buffer layer , 1996, 8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings.

[2]  J. Sack,et al.  A new concept for a non punch through IGBT with MOSFET like switching characteristics , 1989, 20th Annual IEEE Power Electronics Specialists Conference.

[3]  D. Burns,et al.  NPT-IGBT-optimizing for manufacturability , 1996, 8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings.

[4]  T. Laska,et al.  Optimizing the vertical IGBT structure-the NPT concept as the most economic and electrically ideal solution for a 1200 V-IGBT , 1996, 8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings.

[5]  Y. Ishimura,et al.  A high performance IGBT with new n+buffer structure , 1995, Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95.

[6]  W. Kiffe,et al.  A low loss/highly rugged IGBT-generation based on a self aligned process with double implanted n/n/sup +/-emitter , 1994, Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics.