Multi-clock Soc design using protocol conversion

The automated design of SoCs from pre-selected IPs that may require different clocks is challenging because of the following issues. Firstly, protocol mismatches between IPs need to be resolved automatically before IPs are integrated. Secondly, the presence of multiple clocks makes the protocol conversion even more difficult. Thirdly, it is desirable that the resulting integration is correct-by-construction, i.e., the resulting SoC satisfies given system-level specifications. All of these issues have been studied extensively, although not in a unifying manner. In this paper we propose a framework based on protocol conversion that addresses all these issues. We have extensively studied many SoC design problems and show that the proposed methodology is capable of handling them better than other known approaches. A significant contribution of the proposed approach is that it nicely generalizes many existing techniques for formal SoC design and integrates them into a single approach.

[1]  Alberto L. Sangiovanni-Vincentelli,et al.  A methodology for correct-by-construction latency insensitive design , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[2]  Florence Maraninchi,et al.  Argos: an automaton-based synchronous language , 2001, Comput. Lang..

[3]  Orna Kupferman,et al.  Module Checking , 1996, Inf. Comput..

[4]  Samik Basu,et al.  A Module Checking Based Converter Synthesis Approach for SoCs , 2008, 21st International Conference on VLSI Design (VLSID 2008).

[5]  Pascal Fradet,et al.  Adaptor Synthesis for Real-Time Components , 2007, TACAS.

[6]  Alberto L. Sangiovanni-Vincentelli,et al.  Convertibility verification and converter synthesis: two faces of the same coin , 2002, ICCAD 2002.

[7]  Ratnesh Kumar,et al.  A Discrete Event Systems Approach for Protocol Conversion , 1997, Discret. Event Dyn. Syst..

[8]  Girish Bhat,et al.  Efficient on-the-fly model checking for CTL , 1995, Proceedings of Tenth Annual IEEE Symposium on Logic in Computer Science.

[9]  Arcot Sowmya,et al.  Bridge over troubled wrappers:automated interface synthesis , 2004, 17th International Conference on VLSI Design. Proceedings..

[10]  Arcot Sowmya,et al.  A Formal Approach To The Protocol Converter Problem , 2008, 2008 Design, Automation and Test in Europe.

[11]  Alberto L. Sangiovanni-Vincentelli,et al.  Convertibility verification and converter synthesis: two faces of the same coin [IP block interfaces] , 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..