Adaptive routing framework for network on chip architectures
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[1] Hoi-Jun Yoo,et al. Low-power network-on-chip for high-performance SoC design , 2006, IEEE Trans. Very Large Scale Integr. Syst..
[2] Radu Marculescu,et al. DyAD - smart routing for networks-on-chip , 2004, Proceedings. 41st Design Automation Conference, 2004..
[3] Daniel Chillet,et al. DRAFT: Flexible interconnection network for dynamically reconfigurable architectures , 2009, 2009 International Conference on Field-Programmable Technology.
[4] Thilo Pionteck,et al. Applying Partial Reconfiguration to Networks-On-Chips , 2006, 2006 International Conference on Field Programmable Logic and Applications.
[5] Wei Zhang,et al. A NoC Traffic Suite Based on Real Applications , 2011, 2011 IEEE Computer Society Annual Symposium on VLSI.
[6] Ali Ahmadinia,et al. Dynamic interconnection of reconfigurable modules on reconfigurable devices , 2005, IEEE Design & Test of Computers.
[7] Stephen W. Keckler,et al. Regional congestion awareness for load balance in networks-on-chip , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.
[8] Luca Benini,et al. NoC synthesis flow for customized domain specific multiprocessor systems-on-chip , 2005, IEEE Transactions on Parallel and Distributed Systems.
[9] Gu Haiyun. Survey of Dynamically Reconfigurable Network-on-Chip , 2011, 2011 International Conference on Future Computer Sciences and Application.
[10] Lionel M. Ni,et al. The Turn Model for Adaptive Routing , 1992, [1992] Proceedings the 19th Annual International Symposium on Computer Architecture.