A linear time algorithm for wire sizing with simultaneous optimization of interconnect delay and crosstalk noise
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[1] Jason Cong,et al. Simultaneous Driver And Wire Sizing For Performance And Power Optimization* , 1994, IEEE/ACM International Conference on Computer-Aided Design.
[2] Michael E. Wall,et al. Galib: a c++ library of genetic algorithm components , 1996 .
[3] Hideaki Kobayashi,et al. Simultaneous wire sizing and wire spacing in post-layout performance optimization , 1998, Proceedings of 1998 Asia and South Pacific Design Automation Conference.
[4] J. Nash. Equilibrium Points in N-Person Games. , 1950, Proceedings of the National Academy of Sciences of the United States of America.
[5] Christos H. Papadimitriou,et al. On the Complexity of the Parity Argument and Other Inefficient Proofs of Existence , 1994, J. Comput. Syst. Sci..
[6] H. B. Bakoglu,et al. Circuits, interconnections, and packaging for VLSI , 1990 .
[7] Jason Cong,et al. Interconnect-Driven Floorplanning with Fast Global Wiring Planning and Optimization , 2001 .
[8] Charles J. Alpert,et al. Is wire tapering worthwhile? , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).
[9] S. Kakutani. A generalization of Brouwer’s fixed point theorem , 1941 .
[10] C. S. Walker,et al. Capacitance, Inductance, and CrossTalk Analysis , 1990 .
[11] Jason Cong,et al. Wire width planning for interconnect performance optimization , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[12] Martin D. F. Wong,et al. Closed form solution to simultaneous buffer insertion/sizing and wire sizing , 1997, ISPD '97.
[13] Sachin S. Sapatnekar,et al. Wire sizing as a convex optimization problem: exploring the area-delay tradeoff , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[14] T. Sakurai,et al. Simple formulas for two- and three-dimensional capacitances , 1983, IEEE Transactions on Electron Devices.
[15] D. F. Wong,et al. Closed form solutions to simultaneous buffer insertion/sizing and wire sizing , 2001, ACM Trans. Design Autom. Electr. Syst..
[16] Kurt Keutzer,et al. Getting to the bottom of deep submicron , 1998, ICCAD '98.
[17] S. Seki,et al. Analysis of crosstalk in very high-speed LSI/VLSI's using a coupled multiconductor MIS microstrip line model , 1984 .
[18] Yao-Wen Chang,et al. Timing modeling and optimization under the transmission line model , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[19] Adrian Vetta,et al. Nash equilibria in competitive societies, with applications to facility location, traffic routing and auctions , 2002, The 43rd Annual IEEE Symposium on Foundations of Computer Science, 2002. Proceedings..
[20] E. Rasmusen. Games and Information: An Introduction to Game Theory , 2006 .
[21] Robert K. Brayton,et al. Cross-talk noise immune VLSI design using regular layout fabrics , 2001 .
[22] Christos H. Papadimitriou,et al. Algorithms, Games, and the Internet , 2001, ICALP.
[23] S. Seki,et al. Analysis of crosstalk in very high-speed LSI/VLSI's using a coupled multiconductor MIS microstrip line model , 1984, IEEE Transactions on Electron Devices.
[24] Yao-Wen Chang,et al. Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[25] Charlie Chung-Ping Chen,et al. Optimal wire-sizing function with fringing capacitance consideration , 1997, DAC.