Memory Organization for Low-Energy Embedded Systems

[1]  Massoud Pedram,et al.  Low power design methodologies , 1996 .

[2]  Wayne H. Wolf,et al.  Code compression for embedded systems , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[3]  Donald E. Thomas,et al.  Memory modeling for system synthesis , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[4]  Srilatha Manne,et al.  Power and performance tradeoffs using various caching strategies , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

[5]  Gaetano Borriello,et al.  Practical dictionary management for hardware data compression , 1992, CACM.

[6]  Chaitali Chakrabarti,et al.  Memory exploration for low power, embedded systems , 1999, DAC '99.

[7]  Alvin M. Despain,et al.  Cache design trade-offs for power and performance optimization: a case study , 1995, ISLPED '95.

[8]  Jun Yang,et al.  Frequent value compression in data caches , 2000, MICRO 33.

[9]  Luca Benini,et al.  An adaptive data compression scheme for memory traffic minimization in processor-based systems , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[10]  Luca Benini,et al.  Minimizing memory access energy in embedded systems by selective instruction compression , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[11]  Luca Benini,et al.  Code compression architecture for cache energy minimisation in embedded systems , 2002 .

[12]  Nikil D. Dutt,et al.  Access pattern based local memory customization for low power embedded systems , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[13]  Luca Benini,et al.  Hardware-assisted data compression for energy minimization in systems with embedded processors , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[14]  Raminder Singh Bajwa,et al.  Instruction buffering to reduce power in processors for signal processing , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[15]  A. Varadharajan,et al.  A low-cost 300 MHz RISC CPU with attached media processor , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[16]  Kevin D. Kissell.  MIPS16: High-density MIPS for the Embedded Market1 , 1997 .

[17]  Luca Benini,et al.  Layout-driven memory synthesis for embedded systems-on-chip , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[18]  Liam Goudge,et al.  Embedded control problems, Thumb, and the ARM7TDMI , 1995, IEEE Micro.

[19]  Jörg Henkel,et al.  Code compression for low power embedded system design , 2000, Proceedings 37th Design Automation Conference.

[20]  Takao Onoye,et al.  An object code compression approach to embedded processors , 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.

[21]  Trevor N. Mudge,et al.  Evaluation of a high performance code compression method , 1999, MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture.

[22]  Majid Sarrafzadeh,et al.  Memory Segmentation to Exploit Sleep Mode Operation , 1995, 32nd Design Automation Conference.

[23]  James R. Goodman,et al.  Hardware techniques to improve the performance of the processor/memory interface , 1998 .

[24]  Alexandru Nicolau,et al.  Memory Issues in Embedded Systems-on-Chip , 1999 .

[25]  Enrico Macii,et al.  Improving the efficiency of memory partitioning by address clustering , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[26]  Thomas M. Conte,et al.  Compiler-driven cached code compression schemes for embedded ILP processors , 1999, MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture.

[27]  Antonio Gonzalez,et al.  A data cache with multiple caching strategies tuned to different types of locality , 1995, International Conference on Supercomputing.

[28]  Uming Ko,et al.  Energy optimization of multilevel cache architectures for RISC and CISC processors , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[29]  Jang-Soo Lee,et al.  Design and evaluation of a selective compressed memory system , 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).