Future scaling of Si based microelectronics and the role of consortia

Semiconductor technology and its relentless scaling are at the core of many of the revolutionary gains humanity has witnessed in the last few decades. Future scaling options are promising, although complex and costly. Planar, Si-based materials integration for ever smaller devices has matured to heterointegration of non-Si materials today, and rapidly, scaling is moving to the 3rd dimension for devices and interconnects. Patterning technologies are pushing the limits of immersion-based deep UV technologies and are at the cusp of EUV technologies. Looking farther beyond, several options like nano imprint and directed self assembly are emerging to address cost and throughput issues. Functionality per unit area per unit cost continues to be aggressively pushed, and move to 450mm wafer size is along this trend. Concurrent to all these changes, functionally driven scaling - where traditional CMOS/memory elements are combined with non-CMOS devices to realize complex system on a chip (SOC), and perhaps system in a package (SIP) are being pursued. These changes present enormous opportunities for the industry, but are significant transitions to new technologies that require coordination across chip makers, supply chain, design and system houses. Consortia like SEMATECH play a critical role in enabling these transitions. Many infrastructural issues, standards and protocols for successful introduction of new technology transitions to high volume manufacturing are addressed to minimize cost and risk.