Correct-by-Construction Parallelization of Hard Real-Time Avionics Applications on Off-the-Shelf Predictable Hardware

We present the first end-to-end modeling and compilation flow to parallelize hard real-time control applications while fully guaranteeing the respect of real-time requirements on off-the-shelf hardware. It scales to thousands of dataflow nodes and has been validated on two production avionics applications. Unlike classical optimizing compilation, it takes as input non-functional requirements (real time, resource limits). To enforce these requirements, the compiler follows a static resource allocation strategy, from coarse-grain tasks communicating over an interconnection network all the way to individual variables and memory accesses. It controls timing interferences resulting from mapping decisions in a precise, safe, and scalable way.

[1]  Pascal Sainrat,et al.  Mapping hard real-time applications on many-core processors , 2016, RTNS '16.

[2]  Joseph Sifakis,et al.  Rigorous Component-Based System Design Using the BIP Framework , 2011, IEEE Software.

[3]  Marco Caccamo,et al.  A Predictable Execution Model for COTS-Based Embedded Systems , 2011, 2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium.

[4]  Frédéric Boniol,et al.  Multi-task Implementation of Multi-periodic Synchronous Programs , 2011, Discret. Event Dyn. Syst..

[5]  Robert I. Davis,et al.  Response Time Analysis of Synchronous Data Flow Programs on a Many-Core Processor , 2016, RTNS '16.

[6]  Robert de Simone,et al.  On the Scalability of Constraint Solving for Static/Off-Line Real-Time Scheduling , 2015, FORMATS.

[7]  Robert de Simone,et al.  MARTE: a profile for RT/E systems modeling, analysis-and simulation? , 2008, SimuTools.

[8]  Robert de Simone,et al.  Clock-driven distributed real-time implementation of endochronous synchronous programs , 2009, EMSOFT '09.

[9]  Dominic Oehlert,et al.  Automated generation of time-predictable executables on multicore , 2018, RTNS.

[10]  Robert de Simone,et al.  Static Mapping of Real-Time Applications onto Massively Parallel Processor Arrays , 2014, 2014 14th International Conference on Application of Concurrency to System Design.

[11]  Pascal Sainrat,et al.  Automatic WCET Analysis of Real-Time Parallel Applications , 2013, WCET.

[12]  Leslie G. Valiant,et al.  A bridging model for parallel computation , 1990, CACM.

[13]  Mark N. Wegman,et al.  Efficiently computing static single assignment form and the control dependence graph , 1991, TOPL.

[14]  Dumitru Potop-Butucaru,et al.  Integrated Worst-Case Execution Time Estimation of Multicore Applications , 2013, WCET.

[15]  Guang R. Gao,et al.  A comparative study of multiprocessor list scheduling heuristics , 1994, 1994 Proceedings of the Twenty-Seventh Hawaii International Conference on System Sciences.

[16]  Stavros Tripakis,et al.  Defining and translating a "safe" subset of simulink/stateflow into lustre , 2004, EMSOFT '04.

[17]  Jeffrey K. Hollingsworth,et al.  Critical Path Profiling of Message Passing and Shared-Memory Programs , 1998, IEEE Trans. Parallel Distributed Syst..

[18]  Thomas Carle,et al.  From Dataflow Specification to Multiprocessor Partitioned Time-triggered Real-time Implementation , 2015, Leibniz Trans. Embed. Syst..

[19]  Alain Girault,et al.  The ForeC Synchronous Deterministic Parallel Programming Language for Multicores , 2016, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC).

[20]  Alan Burns,et al.  Multi-core Cyclic Executives for Safety-Critical Systems , 2017, SETTA.

[21]  Matthieu Lemerre,et al.  The OASIS Kernel: A Framework for High Dependability Real-Time Systems , 2011, 2011 IEEE 13th International Symposium on High-Assurance Systems Engineering.

[22]  Jakob Engblom,et al.  The worst-case execution-time problem—overview of methods and survey of tools , 2008, TECS.

[23]  M. Masmano,et al.  Xoncrete : a scheduling tool for partitioned real-time systems , 2011 .

[24]  Pascal Raymond,et al.  Parallel code generation of synchronous programs for a many-core architecture , 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[25]  Thomas Carle,et al.  Predicate-aware, makespan-preserving software pipelining of scheduling tables , 2014, TACO.

[26]  Sander Stuijk,et al.  NoC-Based Multiprocessor Architecture for Mixed-Time-Criticality Applications , 2017, Handbook of Hardware/Software Codesign.

[27]  Steven S. Muchnick,et al.  Advanced Compiler Design and Implementation , 1997 .

[28]  Nicolas Halbwachs,et al.  LUSTRE: A declarative language for programming synchronous systems* , 1987 .

[29]  David Broman,et al.  FlexPRET: A processor platform for mixed-criticality systems , 2014, 2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS).

[30]  Robert de Simone,et al.  MARTE: a profile for RT/E systems modeling, analysis-- and simulation ? , 2008, Simutools 2008.

[31]  Jan Reineke,et al.  Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-Critical Embedded Systems , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[32]  Mark Smotherman,et al.  Efficient DAG construction and heuristic calculation for instruction scheduling , 1991, MICRO 24.

[33]  Marc Pouzet,et al.  Clock-directed modular code generation for synchronous data-flow languages , 2008, LCTES '08.

[34]  Pascal Sainrat,et al.  Temporal Isolation of Hard Real-Time Applications on Many-Core Processors , 2016, 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS).

[35]  Alena Simalatsar,et al.  Near-optimal deployment of dataflow applications on many-core platforms with real-time guarantees , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

[36]  Daniel Grund,et al.  Computation takes time, but how much? , 2014, CACM.

[37]  Sanjoy K. Baruah,et al.  Multiprocessor Scheduling for Real-Time Systems , 2015, Embedded Systems.

[38]  Marc Pouzet,et al.  Hard Real Time and Mixed Time Criticality on Off-The-Shelf Embedded Multi-Cores , 2016 .

[39]  Benoît Dupont de Dinechin,et al.  K-Periodic schedules for evaluating the maximum throughput of a Synchronous Dataflow graph , 2012, 2012 International Conference on Embedded Computer Systems (SAMOS).

[40]  Marc Pouzet,et al.  A modular memory optimization for synchronous data-flow languages: application to arrays in a lustre compiler , 2012, LCTES '12.

[41]  Benoît Dupont de Dinechin,et al.  Extended Cyclostatic Dataflow Program Compilation and Execution for an Integrated Manycore Processor , 2013, ICCS.

[42]  B. Ramakrishna Rau,et al.  Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing , 1981, MICRO 14.

[43]  Luciano Lavagno,et al.  Scheduling for Embedded Real-Time Systems , 1998, IEEE Des. Test Comput..

[44]  Nicolas Halbwachs,et al.  LUSTRE: a declarative language for real-time programming , 1987, POPL '87.

[45]  Peng Deng,et al.  A model-based synthesis flow for automotive CPS , 2015, ICCPS.

[46]  Marc Pouzet,et al.  Scade 6: From a Kahn Semantics to a Kahn Implementation for Multicore , 2018, 2018 Forum on Specification & Design Languages (FDL).

[47]  Nicolas Halbwachs,et al.  A synchronous language at work: the story of Lustre , 2005, Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2005. MEMOCODE '05..

[48]  Steven Derrien,et al.  Tightening Contention Delays While Scheduling Parallel Applications on Multi-core Architectures , 2017, ACM Trans. Embed. Comput. Syst..

[49]  Vicki H. Allan,et al.  Software pipelining , 1995, CSUR.

[50]  Silviu S. Craciunas,et al.  Combined task- and network-level scheduling for distributed time-triggered systems , 2016, Real-Time Systems.

[51]  Maryline Chetto Scheduling in Energy Autonomous Objects , 2014 .

[52]  Stavros Tripakis,et al.  From simulink to SCADE/lustre to TTA: a layered approach for distributed embedded applications , 2003, LCTES '03.