Throughput and latency analysis of the Spidergon-Donut interconnection network

The Spidergon-Donut on-chip interconnection network was proposed to interconnect the cores of a 1000+ core chip. In this paper, we derive a queueing model for the Spidergon-Donut, and analyze its throughput and latency in comparison with the commercial Spidergon network on which it is based. Results indicate that the Spidergon-Donut throughput is 3-5 times larger than that of the Spidergon network, for 32-4096 cores and the Spidergon-Donut significantly outperforms the Spidergon in network latency under moderate to large traffic rates. Furthermore, for 1K cores, the average distance of the Spidergon-Donut is one tenth that of the Spidergon.

[1]  Franco P. Preparata,et al.  The cube-connected-cycles: A versatile network for parallel computation , 1979, 20th Annual Symposium on Foundations of Computer Science (sfcs 1979).

[2]  Miltos D. Grammatikakis,et al.  Design of Cost-Efficient Interconnect Processing Units , 2008 .

[3]  Wim Vanderbauwhede,et al.  An analytical performance model for the Spidergon NoC with virtual channels , 2010, J. Syst. Archit..

[4]  Charles E. Leiserson,et al.  Fat-trees: Universal networks for hardware-efficient supercomputing , 1985, IEEE Transactions on Computers.

[5]  Fadi N. Sibai,et al.  Optimal Clustering of Hierarchical Hyper-Ring Multicomputers , 1999, The Journal of Supercomputing.

[6]  Fadi N. Sibai,et al.  A Two-Dimensional Low-Diameter Scalable On-Chip Network for Interconnecting Thousands of Cores , 2012, IEEE Transactions on Parallel and Distributed Systems.

[7]  Fadi N. Sibai Resource Sharing in Networks-on-Chip of Large Many-core Embedded Systems , 2009, 2009 International Conference on Parallel Processing Workshops.

[8]  Fadi N. Sibai,et al.  Design and evaluation of low latency interconnection networks for real-time many-core embedded systems , 2011, Comput. Electr. Eng..

[9]  Sudhakar Yalamanchili,et al.  Interconnection Networks: An Engineering Approach , 2002 .

[10]  Alain Greiner,et al.  Micro-network for SoC: implementation of a 32-port SPIN network , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[11]  Franco P. Preparata,et al.  The cube-connected-cycles: A versatile network for parallel computation , 1979, 20th Annual Symposium on Foundations of Computer Science (sfcs 1979).

[12]  Martin Hopkins,et al.  Synergistic Processing in Cell's Multicore Architecture , 2006, IEEE Micro.

[13]  William J. Dally,et al.  Principles and Practices of Interconnection Networks , 2004 .

[14]  Fadi N. Sibai,et al.  The hyper-ring network: a cost-efficient topology for scalable multicomputers , 1998, SAC '98.

[15]  Wang Li-fang,et al.  Networks on Chips , 2005 .

[16]  M. Coppola,et al.  Spidergon: a novel on-chip communication network , 2004, 2004 International Symposium on System-on-Chip, 2004. Proceedings..

[17]  Nicola Concer,et al.  Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[18]  William J. Dally Enabling Technology for On-Chip Interconnection Networks , 2007, First International Symposium on Networks-on-Chip (NOCS'07).