Twin Butterfly High Throughput Parallel Architecture FFT Algorithm

A novel parallel memory accessing for decimation-in-time twin butterfly parallel architecture radix-4 FFT algorithm is proposed, which is based on "in-place" principle and allows conflict-free access to the 8 operands needed for calculation of the twin butterfly distributed over 8 parallel memory modules. Data and twiddle factor address generation algorithm and store scheme are described detailed. Comparison with conventional methods is also presented.