Fine-Grained Partial Runtime Reconfiguration on Virtex-5 FPGAs

The architecture of Xilinx FPGAs, has changed remarkable with respect to their ability to implement runtime reconfigurable systems throughout the last generations. This paper will discuss these changes and reveal an on-FPGA communication architecture that is especially tailored to Xilinx Virtex-5 FPGAs. With this architecture, modules can be integrated in a two-dimensional grid with more than a hundred of individual tiles while allowing a throughput of several GB/s to reconfigurable modules.

[1]  Marek Gorgon,et al.  PixelStreams-based implementation of videodetector , 2007 .

[2]  Steve Douglass,et al.  The next generation 65-nm FPGA , 2006, 2006 IEEE Hot Chips 18 Symposium (HCS).

[3]  Jürgen Teich,et al.  A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAs , 2009, FPGA '09.

[4]  Wayne Luk,et al.  Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration , 2007, 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007).

[5]  Jürgen Teich,et al.  Minimizing Internal Fragmentation by Fine-Grained Two-Dimensional Module Placement for Runtime Reconfiguralble Systems , 2009, 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines.