Design of low power 3D hybrid memory by non-volatile CBRAM-crossbar with block-level data-retention

As one of the newly introduced resistive random access memory (ReRAM) devices, this paper has shown an in-depth study of conductive-bridging random access memory (CBRAM) for non-volatile memory (NVM) computing. Firstly, a CBRAM-crossbar based memory is evaluated with accurate physical-level model and circuit-level characterization. It is then deployed as NVM component with a 3D hybrid integration of SRAM/DRAM, where one layer of CBRAM-crossbar is designed for data-retention under power gating to reduce leakage power from SRAM/DRAM at other layers. Moreover, a block-level data-retention scheme is designed to only write back dirty data from SRAM/DRAM to CBRAM-crossbar. When compared to the hybrid memory using phase-change random access memory (PCRAM) as data-retention, our CBRAM-based hybrid memory achieves 16x faster migration time and 4x less migration power for hibernating transition. When compared to the FeRAM-based bit-wise data-retention, our approach also achieves 17x smaller area and 8x smaller power under the same data migration speed.

[1]  Evert Seevinck,et al.  Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM's , 1991 .

[2]  Chakravarthy Gopalan,et al.  Demonstration of Conductive Bridging Random Access Memory (CBRAM) in Logic CMOS Process , 2010, 2010 IEEE International Memory Workshop.

[3]  Masahiro Koga,et al.  First Prototype of a Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells , 2010, 2010 International Conference on Field Programmable Logic and Applications.

[4]  Yoshihiro Ueda,et al.  A 64Mb MRAM with clamped-reference and adequate-reference schemes , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[5]  Xiaoxia Wu,et al.  Hybrid cache architecture with disparate memory technologies , 2009, ISCA '09.

[6]  Gabriel H. Loh,et al.  3D-Stacked Memory Architectures for Multi-core Processors , 2008, 2008 International Symposium on Computer Architecture.

[7]  Yuan Xie,et al.  PCRAMsim: System-level performance, energy, and area modeling for Phase-Change RAM , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[8]  Yuan Xie,et al.  3D memory stacking for fast checkpointing/restore applications , 2010, 2010 IEEE International 3D Systems Integration Conference (3DIC).

[9]  Wei Hwang,et al.  Distributed data-retention power gating techniques for column and row co-controlled embedded SRAM , 2005, 2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05).

[10]  Heng-Yuan Lee,et al.  A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability , 2011, 2011 IEEE International Solid-State Circuits Conference.

[11]  Jun Yang,et al.  Phase-Change Technology and the Future of Main Memory , 2010, IEEE Micro.

[12]  M. Kozicki,et al.  Quantized Conductance in $\hbox{Ag/GeS}_{2}/\hbox{W}$ Conductive-Bridge Memory Cells , 2012, IEEE Electron Device Letters.

[13]  David A. Patterson,et al.  Computer Architecture, Fifth Edition: A Quantitative Approach , 2011 .

[14]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[15]  Jan M. Rabaey,et al.  SRAM leakage suppression by minimizing standby supply voltage , 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

[16]  Gerhard Müller,et al.  A Nonvolatile 2-Mbit CBRAM Memory Core Featuring Advanced Read and Program Control , 2007, IEEE Journal of Solid-State Circuits.

[17]  A. Suzuki,et al.  A 65nm low-power embedded DRAM with extended data-retention sleep mode , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[18]  Paul Marchal,et al.  3D integration: Circuit design, test, and reliability challenges , 2010, 2010 IEEE 16th International On-Line Testing Symposium.

[19]  William Song,et al.  Negative-resistance read and write schemes for STT-MRAM in 0.13µm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[20]  Narayan Srinivasa,et al.  A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications. , 2012, Nano letters.

[21]  Shimeng Yu,et al.  Compact Modeling of Conducting-Bridge Random-Access Memory (CBRAM) , 2011, IEEE Transactions on Electron Devices.