SCL 180nm CMOS foundry: High reliability ASIC design for aerospace applications

Semi-Conductor Laboratory (SCL) Fab. has been upgraded to 8" wafer fab to support 180 nm CMOS process made available by M/s. Tower Semiconductor Ltd, Israel. This tutorial describes SCL foundry process features and capabilities. The tutorial will cover SCL Fab base line technology features, analog process modules, digital standard cell library for core and I/Os and memory modules. End to end design flow of digital and mixed signal ASICs with case-study of recently completed ASIC designs along with EDA tools will be covered in this tutorial. SCL Packaging, testing and qualification capabilities will also be addressed. This tutorial will also cover the role of ASICs in various aerospace applications like remote sensing (microwave and optical), communication, navigation etc. Space radiation environment and its effect on electronics devices will be discussed in tutorial. Methodologies for design of Highreliability ASIC with various radiation mitigation techniques will be covered in tutorial. Radiation hardening by design (RHBD) and its implementation aspects will also be suitably addressed. This tutorial will further cover case studies of On Board Controller (OBC-1.1) Digital ASIC and Addressable Synchronous Differential Receiver (ASDR) mixed signal ASIC. Both these ASICs have been fabricated on 180 nm CMOS process with front-end design by SAC and back-end design by SCL.