Antirandom Test Vectors for BIST in Hardware/Software Systems

Antirandom testing has proved useful in a series of empricial evaluations. It improves the fault-detection capability of random testing by employing the location information of previously executed test cases. In antirandom testing we select test pattern (test vector) such that it is as different as possible from all the previous executed test cases. Unfortunately, this method essentially requires enumeration of the input space and computation of each input vector when used on an arbitrary set of existing test data. This avoids scale-up to large test sets and (or) long input vectors. In this paper, we propose a new algorithm for antirandom test generation that is computationally feasible for BIST (Built In Self Test) tests. As the fitness function we use Maximal Minimal Hamming Distance (MMHD) rather than standard Hamming distance as is used in the classical approach. This allows to generate the most efficient test vectors in term of weighted number of generated k-bits tuples. Experimental results are given to evaluate the performance of the new approach.

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