Buffer insertion after layer assignment considering process variation based on a systematic ILD model

We present an approach to buffer insertion after layer assignment, considering process variation based on a systematic ILD model. There are three contributions mentioned in the paper: Firstly, a systematic ILD model is introduced to compute the process variation systematically, in order to get accurate timing delay. Secondly, a buffer insertion algorithm considering process variation is presented, which leads to a more accurate results and makes the performance more close to the real manufactured chip, avoiding excessive conservativeness caused by the worst case method. Third, the phase of buffer insertion is executed after layer assignment, so that different electronic parameters and wire density of distinct layers are concerned, and it is better than the traditional solution, which regarded those parameters as constants. Experimental results demonstrate that our approach can decrease the number of buffers about 50% less than the worst case when comparing with the results of L.P.P.P. Van Ginneken (Proc. Int. Symp. on Circuits and Sys., pp. 865-868, Dec. 1990).