In this work, we compare different modeling approaches typically adopted to address current transport in polysilicon-channel MOSFETs. The analysis is focused on cylindrical gate-all-around devices with deca-nanometer dimension, due to the strong relevance recently gained by such devices in the field of 3-D NAND Flash memories. Pure drift-diffusion simulations under the effective medium approximation are compared to simulations accounting for polysilicon grains and grain boundaries, either keeping pure drift-diffusion transport or mixing intra-grain drift-diffusion with inter-grain thermionic emission. Some nonnegligible differences among the predictions of the three modeling approaches are highlighted and explained as a function of the device working regime, temperature and average size of the polysilicon grains. Results represent an important step towards a better understanding and a better extraction of the parameters of polysilicon-channel devices.