Cycle accurate binary translation for simulation acceleration in rapid prototyping of SoCs

The application of a cycle accurate binary translator for rapid prototyping of SoCs is presented. This translator generates code to run on a rapid prototyping system consisting of a VLIW processor and FPGAs. The generated code is annotated with information that triggers cycle generation for the hardware in parallel with the execution of the translated program. The VLIW processor executes the translated program whereas the FPGAs contain the hardware for the parallel cycle generation and the bits interface that adapts the bits of the VLIW processor to the SoC bits of the emulated processor core.

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