A testable parity conservative gate in quantum-dot cellular automata

Abstract There are important challenges in current VLSI technology such as feature size. New technologies are emerging to overcome these challenges. One of these technologies is quantum-dot cellular automata (QCA) but it also has some disadvantages. One of the very important challenges in QCA is the occurrence of faults due to its very small area. There are different ways to overcome this challenge, one of which is the testable logic gate. There are two types of testable gate; reversible gate, and conservative gate. We propose a new testable parity conservative gate in this paper. This gate is simulated with QCADesigner and compared with previous structures. Power dissipation of proposed gate investigated using QCAPro simulator as an accurate power estimator tool.

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