In many Digital Signal Processing (DSP) modules, increasing the number of pipelining stages to achieve higher throughput may break the module functionality if a feedback-loop exists in the algorithm. This paper addresses a novel algorithmic-level technique to modify implementation of feedback loops to allow deeper pipelining while sustaining the module functionality. An equivalent model for a first-order Infinite Impulse Response (IIR) filter can be obtained by a cascade model including a higher order repeated-pole IIR filter followed by a Finite Impulse Response (FIR) filter. The order of the repeated-pole IIR filters, and hence the number of pipelining stages can be chosen to meet the Fmax requirements. The model is further developed to include a class of mathematical recursive functions to cover many different DSP applications.
[1]
Michael Francis.
Infinite Impulse Response Filter Structures in Xilinx FPGAs
,
2008
.
[2]
Keshab K. Parhi,et al.
Pipeline interleaving and parallelism in recursive digital filters. II. Pipelined incremental block filtering
,
1989,
IEEE Trans. Acoust. Speech Signal Process..
[3]
Gregory Beylkin.
On Factored FIR Approximation of IIR Filters
,
1995
.
[4]
Izzet Kale,et al.
DSP System Design: Complexity Reduced IIR Filter Implementation for Practical Applications
,
2003
.
[5]
B. Anderson,et al.
Optimizing FIR approximation for discrete-time IIR filters
,
2003,
IEEE Signal Processing Letters.