High-level power estimation of VLSI systems

The goal of this paper is to present an innovative conceptual framework suitable for achieving accurate and efficient estimation of power dissipation for data-path intensive architectures described at RT and behavioral levels. The aim is to provide the designer with the capability of analyzing different solutions in the architectural design space, before the synthesis tasks. The proposed methodology addresses all the elements composing a typical data-path architecture, such as storage units, functional units and multiplexers. The paper includes experimental results demonstrating the validity of the proposed approach.

[1]  Daniel D. Gajski,et al.  Area and performance estimation from system-level specifications , 1992 .

[2]  Farid N. Najm,et al.  A survey of power estimation techniques in VLSI circuits , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[3]  Anantha P. Chandrakasan,et al.  Minimizing power consumption in digital CMOS circuits , 1995, Proc. IEEE.

[4]  Cristina Silvano,et al.  A conceptual analysis framework for low power design of embedded systems , 1996, 1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon.

[5]  Sharad Malik,et al.  A Survey of Optimization Techniques Targeting Low Power VLSI Circuits , 1995, 32nd Design Automation Conference.

[6]  Paul E. Landman,et al.  High-level power estimation , 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.

[7]  Jan M. Rabaey,et al.  Architectural power analysis: The dual bit type method , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[8]  Donatella Sciuto,et al.  Tosca: A Pragmatic Approach To Co-Design Automation Of Control-Dominated Systems , 1996 .

[9]  Jan M. Rabaey,et al.  Power estimation for high level synthesis , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.