Hybrid circuit-switched network for on-chip communication in large-scale chip-multiprocessors

Large-scale chip-multiprocessors (CMPs) need a scalable communication structure characterized by low cost, low power, and high performance to meet their on-chip communication requirements. This paper presents a hybrid circuit-switched (HCS) network for on-chip communication in the large-scale CMPs. The HCS network, which is Advanced Microcontroller Bus Architecture (AMBA) compatible, is composed of bufferless switches, pipeline channels, and network interfaces. Furthermore, packets are transferred in a hybrid transmission scheme. If a message has only one packet, the transmission scheme for this message is packet switching. Conversely, if a message contains multiple packets, the transmission scheme for this message is circuit switching. We evaluate HCS networks with different channel depths and then compare the HCS network with the Stanford elastic buffer (EB) network. Our results show that the HCS network with two-depth channel requires 83% less power and occupies 32% less area compared with the EB network. Furthermore, under maximum frequency and single traffic, the HCS network with two-depth channel provides 37% lower zero-load latency, 390% higher maximum throughput per unit power, and 19% higher maximum throughput per unit area compared with the EB network.

[1]  George Michelogiannakis,et al.  Router designs for elastic buffer on-chip networks , 2009, Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis.

[2]  Jean-Didier Legat,et al.  A hybrid router combining circuit switching and packet switching with bus architecture for on-chip networks , 2010, Proceedings of the 8th IEEE International NEWCAS Conference 2010.

[3]  Shekhar Y. Borkar,et al.  Design challenges of technology scaling , 1999, IEEE Micro.

[4]  Anshul Kumar,et al.  Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures , 2007, TODE.

[5]  Nan Jiang,et al.  Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks , 2011, IEEE Computer Architecture Letters.

[6]  Doug Burger,et al.  Implementation and Evaluation of On-Chip Network Architectures , 2006, 2006 International Conference on Computer Design.

[7]  Natalie D. Enright Jerger,et al.  SCARAB: A single cycle adaptive routing and bufferless network , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[8]  Ken Mai,et al.  The future of wires , 2001, Proc. IEEE.

[9]  Onur Mutlu,et al.  A case for bufferless routing in on-chip networks , 2009, ISCA '09.

[10]  Federico Silla,et al.  A comparative study of arbitration algorithms for the Alpha 21364 pipelined router , 2002, ASPLOS X.

[11]  George Michelogiannakis,et al.  Elastic-buffer flow control for on-chip networks , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[12]  Kiyoung Choi,et al.  Instruction set synthesis with efficient instruction encoding for configurable processors , 2007, TODE.

[13]  Pedro López,et al.  Reducing Packet Dropping in a Bufferless NoC , 2008, Euro-Par.

[14]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[15]  Henry Hoffmann,et al.  Evaluation of the Raw microprocessor: an exposed-wire-delay architecture for ILP and streams , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..

[16]  Timothy Mattson,et al.  A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[17]  George Michelogiannakis,et al.  Evaluating Elastic Buffer and Wormhole Flow Control , 2011, IEEE Transactions on Computers.

[18]  George Michelogiannakis,et al.  Evaluating Bufferless Flow Control for On-chip Networks , 2010, 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip.

[19]  Mikko H. Lipasti,et al.  Circuit-Switched Coherence , 2008 .

[20]  Radu Marculescu,et al.  Traffic analysis for on-chip networks design of multimedia applications , 2002, DAC '02.

[21]  William J. Dally,et al.  Research Challenges for On-Chip Interconnection Networks , 2007, IEEE Micro.

[22]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[23]  Radu Marculescu,et al.  On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches , 2007, TODE.

[24]  Sriram R. Vangal,et al.  A 5-GHz Mesh Interconnect for a Teraflops Processor , 2007, IEEE Micro.

[25]  David Wentzlaff,et al.  Processor: A 64-Core SoC with Mesh Interconnect , 2010 .

[26]  Martti Forsell,et al.  A Scalable High-Performance Computing Solution for Networks on Chips , 2002, IEEE Micro.

[27]  Mohammad Arjomand,et al.  A hybrid packet-circuit switched on-chip network based on SDM , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[28]  Coniferous softwood.  GENERAL TERMS , 2003 .

[29]  Pedro López,et al.  A high performance router architecture for interconnection networks , 1996, Proceedings of the 1996 ICPP Workshop on Challenges for Parallel Processing.

[30]  Donghui Guo,et al.  Hybrid circuit-switched NOC for low cost on-chip communication , 2012, Anti-counterfeiting, Security, and Identification.

[31]  K.M. Al-Tawil,et al.  A survey and comparison of wormhole routing techniques in a mesh networks , 1997, IEEE Network.