Compact modeling of offset sources in vertical hall-effect devices

Vertical Hall-effect devices are CMOS integrated sensors designed for the measurement of magnetic field in the plane of the chip. In such devices, systematic offset is a major issue which limits their performance. We recently developed a design-oriented compact model for such devices. In this paper, the model is improved and used to study the main features of the offset. There are two main phenomena that induce offset in the sensor: sensor imperfections (process deviation, mechanical stress...) which can be modeled by contact misalignments, and the modulation of the space charge region at the N-well/P-sub junction. Offset is modeled through 4 parameters which are extracted from offset measurement, and the model is validated with experimental results.

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