An emitter coupled logic (ECL) 100 K compatible output buffer circuit fabricated in a submicrometer CMOS-only process is presented. High speed (0.9-ns delay) and sufficient precision are achieved through the use of a novel circuit principle. Negative feedback and an error correction technique are applied in such a way that external components and/or additional power supplies are not required. Aspects of stability and accuracy are investigated and simulation results are discussed to explain the circuit technique. The actual design and practical aspects of it, such as layout, implementation in silicon, and technology features, are shown. Measured and simulation results, showing the good performance of the ECL output buffer across a wide range of capacitive loading, are presented. >
[1]
E. De Man,et al.
A 2/spl mu/m Cmos Digital Adaptive Equalizer Chip For QAM Digital Radio Modems
,
1988
.
[2]
E. Seevinck,et al.
CMOS subnanosecond true-ECL output buffer
,
1989,
Symposium 1989 on VLSI Circuits.
[4]
Stanley E. Schuster,et al.
Fast CMOS ECL receivers with 100-mV worst-case sensitivity
,
1988
.
[5]
A. Jonkers,et al.
A 1M SRAM with full CMOS cells fabricated in a 0.7µm technology
,
1987,
1987 International Electron Devices Meeting.
[6]
R. L. Franch,et al.
A 6.2 ns 64Kb CMOS RAM with ECL interfaces
,
1988,
Symposium 1988 on VLSI Circuits.