Emerging applications require computing platforms to extract task-relevant information from increasingly large amounts of data. These requirements place stringent constraints on energy efficiency, throughput, latency, and for certain data types, security and privacy of computing platforms. Traditionally, silicon CMOS scaling has been relied upon to meet these energy and delay constraints. However, the energy and delay benefits achievable via scaling are diminishing. Increased vulnerability to various sources of variations (e.g., process, voltage) further exacerbates these energy and speed challenges.