A novel architecture for VLSI implementation of the 2-D DCT/IDCT

The implementation of a 8*8 two-dimensional forward/inverse discrete cosine transform (DCT) chip is presented. The structure is highly regular and modular and the DCT computation is carried out using registers and adders only. A fully pipelined structure based on a new approach for serial arithmetic computation allows a high throughput capability (i.e., up to 40 MHz). The chip is fully functional and is being employed in the Alcatel Telettra HDTV (high definition television) codec. Fabricated in 1 eta m double-metal CMOS technology by LSI Logic, the chip uses approximately 57000 transistors which occupy a 218-pad die area of 8.6 mm*8.6 mm (56 pads are used).<<ETX>>