Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment

With the growing size of modern designs and more strict time-to-market constraints, design errors can unavoidably escape pre-silicon verification and reside in silicon prototypes. Due to those errors and faults in the fabrication process, silicon debug has become a necessary step in the digital integrated circuit design flow. Embedded hardware blocks, such as scan chains and trace buffers, provide a means to acquire data of internal signals in real time for debugging. However, the amount of the data is limited compared to pre-silicon debugging. This paper presents an automated software solution to analyze this sparse data to detect suspects of the failure in both the spatial and temporal domain. It also introduces a technique to automate the configuration process for trace-buffer-based hardware in order to acquire helpful information for debugging the failure. The technique takes the hardware constraints into account and identifies alternatives for signals not part of the traceable set so that their values can be restored by implications. The experiments demonstrate the effectiveness of the proposed software solution in terms of run-time and resolution.

[1]  Kai Yang,et al.  Diagnosing Silicon Failures Based on Functional Test Patterns , 2006, Seventh International Workshop on Microprocessor Test and Verification (MTV'06).

[2]  Joao Marques-Silva,et al.  GRASP-A new search algorithm for satisfiability , 1996, Proceedings of International Conference on Computer Aided Design.

[3]  Ismet Bayraktaroglu,et al.  Microprocessor silicon debug based on failure propagation tracing , 2005, IEEE International Conference on Test, 2005..

[4]  Tracy Larrabee,et al.  Test pattern generation using Boolean satisfiability , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Rolf Drechsler,et al.  Post-verification debugging of hierarchical designs , 2005, ICCAD 2005.

[6]  Michael Miller,et al.  Emulation verification of the Motorola 68060 , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

[7]  Nur A. Touba,et al.  Automated Selection of Signals to Observe for Efficient Silicon Debug , 2009, 2009 27th IEEE VLSI Test Symposium.

[8]  Alan J. Hu,et al.  BackSpace: Formal Analysis for Post-Silicon Debug , 2008, 2008 Formal Methods in Computer-Aided Design.

[9]  Andreas G. Veneris Fault diagnosis and logic debugging using Boolean satisfiability , 2003, Proceedings. 4th International Workshop on Microprocessor Test and Verification - Common Challenges and Solutions.

[10]  Joao Marques-Silva,et al.  GRASP: A Search Algorithm for Propositional Satisfiability , 1999, IEEE Trans. Computers.

[11]  Karem A. Sakallah,et al.  GRASP—a new search algorithm for satisfiability , 1996, ICCAD 1996.

[12]  Masahiro Fujita,et al.  Modeling the unknown! Towards model-independent fault and error diagnosis , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[13]  Niklas Sörensson,et al.  An Extensible SAT-solver , 2003, SAT.

[14]  Qiang Xu,et al.  Trace signal selection for visibility enhancement in post-silicon validation , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[15]  Joao Marques-Silva,et al.  Spatial and temporal design debug using partial MaxSAT , 2009, GLSVLSI '09.

[16]  Kwang-Ting Cheng,et al.  Safety property verification using sequential SAT and bounded model checking , 2004, IEEE Design & Test of Computers.

[17]  Bashir M. Al-Hashimi,et al.  Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[18]  Alberto L. Sangiovanni-Vincentelli,et al.  A survey of techniques for formal verification of combinational circuits , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

[19]  Leendert M. Huisman Diagnosing arbitrary defects in logic designs using single location at a time (SLAT) , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  Andreas G. Veneris,et al.  Design rewiring using ATPG , 2002, Proceedings. International Test Conference.

[21]  Sharad Malik,et al.  Chaff: engineering an efficient SAT solver , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[22]  Sharad Malik,et al.  On Solving the Partial MAX-SAT Problem , 2006, SAT.

[23]  Sean Safarpour,et al.  Abstraction and refinement techniques in automated design debugging , 2007 .

[24]  Nur A. Touba,et al.  Survey of Test Vector Compression Techniques , 2006, IEEE Design & Test of Computers.

[25]  Qiang Xu,et al.  On Signal Selection for Visibility Enhancement in Trace-Based Post-Silicon Validation , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[26]  Sean Safarpour,et al.  Trace Compaction using SAT-based Reachability Analysis , 2007, 2007 Asia and South Pacific Design Automation Conference.

[27]  R. D. Blanton,et al.  Defect Modeling Using Fault Tuples , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[28]  W. Kent Fuchs,et al.  A deductive technique for diagnosis of bridging faults , 1997, ICCAD 1997.

[29]  Sharad Malik,et al.  Toward formalizing a validation methodology using simulation coverage , 1997, DAC.

[30]  Rolf Drechsler,et al.  Using unsatisfiable cores to debug multiple design errors , 2008, GLSVLSI '08.

[31]  Nicola Nicolici,et al.  Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation , 2008, 2008 Design, Automation and Test in Europe.

[32]  Satish Narayanasamy,et al.  Patching Processor Design Errors with Programmable Hardware , 2007, IEEE Micro.

[33]  Nicola Nicolici,et al.  Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.