Parallel LDPC Decoding on a Network-on-Chip Based Multiprocessor Platform
暂无分享,去创建一个
[1] Gerhard Fettweis,et al. A High-Throughput Programmable Decoder for LDPC Convolutional Codes , 2007, 2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP).
[2] A. Blanksby,et al. A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder , 2001, IEEE J. Solid State Circuits.
[3] Norbert Wehn,et al. Network-on-chip-centric approach to interleaving in high throughput channel decoders , 2005, 2005 IEEE International Symposium on Circuits and Systems.
[4] Amer Baghdadi,et al. Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder , 2008, 2008 45th ACM/IEEE Design Automation Conference.
[5] Robert G. Gallager,et al. Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.
[6] A. J. Blanksby,et al. A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder , 2001, IEEE J. Solid State Circuits.
[7] B. Nikolic,et al. Architectures and implementations of low-density parity check decoding algorithms , 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..
[8] Frank Kienle,et al. Low Complexity LDPC Code Decoders for Next Generation Standards , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.
[9] Hideki Imai,et al. Reduced complexity iterative decoding of low-density parity check codes based on belief propagation , 1999, IEEE Trans. Commun..
[10] Leonel Sousa,et al. Parallel LDPC Decoding on the Cell/B.E. Processor , 2008, HiPEAC.
[11] W. Dally,et al. Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[12] Narayanan Vijaykrishnan,et al. Implementing LDPC decoding on network-on-chip , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.
[13] Leonel Sousa,et al. Massive parallel LDPC decoding on GPU , 2008, PPoPP.
[14] Guido Masera,et al. Implementation of a Flexible LDPC Decoder , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.
[15] J.P. Derutin,et al. Design of a Scalable Network of Communicating Soft Processors on FPGA , 2007, 2006 International Workshop on Computer Architecture for Machine Perception and Sensing.
[16] Naresh R. Shanbhag,et al. High-throughput LDPC decoders , 2003, IEEE Trans. Very Large Scale Integr. Syst..
[17] Gerhard Fettweis,et al. Towards a GBit/s Programmable Decoder for LDPC Convolutional Codes , 2007, 2007 IEEE International Symposium on Circuits and Systems.