On the mapping of massively parallel processors onto finite element graphs

Abstract Massively parallel processors have been built and some are commercially available. Efficient solution of finite element problems on these machines requires minimizing interprocessor communication bandwidth. This is achieved by mapping adjacent generalized elements as far as possible onto directly connected processors. When the topology of the multiprocessor embeds the communication structure of the finite element mesh, this mapping problem becomes similar to the problem of matching two graphs. However, realistic finite element meshes which include several discretization patterns and a variety of local refinement procedures do not result in graphs that exactly match the wiring of a parallel processor. For this reason, we concentrate here on efficient heuristics that produce a mapping that can minimize the overall communication cost and/or communication bandwidth. Two algorithms are presented, one for MIMD machines and another for SIMD computers. It is shown that over a trivial mapping and with a quite reasonable complexity, both algorithms can significantly reduce the cost/bandwidth of communication of a massively parallel processor.