In the trough silicon via (TSV) structure for 3-dimentional integration (3DI), large thermal-mechanical stress acts in the BEOL layer caused by the mismatch in thermal expansion coefficient (CTE) of the TSV materials. The resulting high-stress region is thought to be the critical point for the initiation of the cracking or the de-lamination that affects the mechanical reliability. In this study, the stress of multi-stacked thin Si wafers composed of copper TSV and copper/low-k BEOL structure was analyzed by the finite element method (FEM), aiming to reduce the stress of LSI devices of 3D-IC. The results of sensitivity analysis using design of experiment (DOE) indicated that the thickness of the adhesive layer is the key factor for the structural integration of TSV design. It is suggested that the wafer-on-a-wafer (WOW) process has reliability about 1.5 to 1.75 times higher in the TSV structure with BEOL interconnects.