Role of interface layer in stress-induced leakage current in high-k/metal-gate dielectric stacks

The impact of the Silica-based interface layer (IL) thickness on stress induced leakage current (SILC) on highk/metal-gate transistors is studied at various constant voltage stresses (CVS) and at various temperatures. It is shown that high-k/metal-gate transistors reliability can be greatly improved with interface layer optimization.