Performance evaluation of CNFET-based logic gates

As the physical gate length of current devices is reduced to below 65 nm, effects (such as large parametric variations and increase in leakage current) have caused the I-V characteristics to be substantially depart from those commonly associated with traditional MOSFETs, thus impeding the efficient development and manufacturing of devices at deep submicro/nano scales. Carbon Nanotube Field Effect Transistors (CNFETs) have received widespread attention, as one of the promising technologies for replacing MOSFETs at the end of the Technology Roadmap. This paper presents a detailed simulation-based assessment of circuit performance of this technology and compares it to conventional MOSFETs; the designs of different logic gates and the full adder circuit are simulated under the same minimum gate length and different operational conditions. It is shown that the power-delay product (PDP) and the leakage power for the CNFET based gates are lower than the MOSFET based logic gates by 100 to 150 times, respectively. The CNFET based logic gates demonstrate good functionality even at a 0.3 V power supply (while MOSFET based gates fail at 0.5 V).

[1]  E. L. Harder,et al.  The Institute of Electrical and Electronics Engineers, Inc. , 2019, 2019 IEEE International Conference on Software Architecture Companion (ICSA-C).

[2]  M. Radosavljevic,et al.  Drain voltage scaling in carbon nanotube transistors , 2003, cond-mat/0305570.

[3]  H. Wong,et al.  A Circuit-Compatible SPICE model for Enhancement Mode Carbon Nanotube Field Effect Transistors , 2006, 2006 International Conference on Simulation of Semiconductor Processes and Devices.

[4]  Mark S. Lundstrom,et al.  Performance analysis and design optimization of near ballistic carbon nanotube field-effect transistors , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[5]  S. Datta,et al.  Predicted Performance Advantages of Carbon Nanotube Transistors with Doped Nanotubes as Source/Drain , 2003, cond-mat/0309039.

[6]  Kaushik Roy,et al.  Low-Power CMOS VLSI Circuit Design , 2000 .

[7]  H.-S. Philip Wong,et al.  First Demonstration of AC Gain From a Single-walled Carbon Nanotube Common-Source Amplifier , 2006, 2006 International Electron Devices Meeting.

[8]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[9]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[10]  R. Chau,et al.  Benchmarking nanotechnology for high-performance and low-power logic transistor applications , 2004, IEEE Transactions on Nanotechnology.

[11]  Mark Horowitz,et al.  Scaling, Power and the Future of CMOS , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

[12]  A. Chandrakasan,et al.  Leakage in Nanometer CMOS Technologies (Series on Integrated Circuits and Systems) , 2005 .

[13]  C. Sarkar,et al.  Study of the tunnelling initiated leakage current through the carbon nanotube embedded gate oxide in metal oxide semiconductor structures , 2008, Nanotechnology.

[14]  William J. Bowhill,et al.  Design of High-Performance Microprocessor Circuits , 2001 .