Low-voltage, low-power circuits for data communication systems

Low-Voltage, Low-Power Circuits for Data Communication Systems. (December 2003) Mingdeng Chen, B.S., National University of Defense Technology, P. R. China; M.S., National University of Defense Technology, P. R. China; Chair of Advisory Committee: Dr. Jose Silva-Martinez There are growing industrial demands for low-voltage supply and low-power consumption circuits and systems. This is especially true for very high integration level and very large scale integrated (VLSI) mixed-signal chips and system-on-a-chip. It is mainly due to the limited power dissipation within a small area and the costs related to the packaging and thermal management. In this research work, two low-voltage, low-power integrated circuits used for data communication systems are introduced. The first one is a high performance continuoustime linear phase filter with automatic frequency tuning. The filter can be used in hard disk driver systems and wired communication systems such as 1000Base-T transceivers. A pseudo-differential operational transconductance amplifier (OTA) based on transistors operating in triode region is used to achieve a large linear signal swing with low-voltage supplies. A common-mode (CM) control circuit that combines common-mode feedback (CMFB), common-mode feedforward (CMFF), and adaptivebias has been proposed.

[1]  Y. Wang,et al.  A 150 MHz continuous-time seventh order 0.05/spl deg/ equiripple linear phase filter , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[2]  Wonchan Kim,et al.  A 1 . 5V , 4-MHz CMOS Continuous-Time Filter with a Single-Integrator Based Tuning , 1998 .

[3]  B. Young Enhanced LVDS for signaling on the RapidIO/sup TM/ interconnect architecture , 2000, IEEE 9th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.00TH8524).

[4]  R. Castello,et al.  An eighth-order CMOS lowpass filter with 30-120 Mhz tuning range and programmable boost , 2001, Proceedings of the 26th European Solid-State Circuits Conference.

[5]  Robert G. Meyer,et al.  Analysis and Design of Analog Integrated Circuits , 1993 .

[6]  William Liu,et al.  MOSFET Models for SPICE Simulation: Including BSIM3v3 and BSIM4 , 2001 .

[7]  William Martin Snelgrove,et al.  A balanced 0.9- mu m CMOS transconductance-C filter tunable over the VHF range , 1992 .

[8]  Fred J. Taylor,et al.  Electronic filter design handbook : LC, active, and digital filters , 1988 .

[9]  Yichuang Sun,et al.  Continuous-Time Active Filter Design , 1998 .

[10]  Changsik Yoo,et al.  A /spl plusmn/1.5-V, 4-MHz CMOS continuous-time filter with a single-integrator based tuning , 1998 .

[11]  K. Martin,et al.  Design of signal flow graph (SFG) active filters , 1978 .

[12]  David A. Johns,et al.  Analog Integrated Circuit Design , 1996 .

[13]  M. S. Ghausi,et al.  Design of high-order active filters in integrated circuits , 1978 .

[14]  Kenneth R. Laker,et al.  Multiple-Loop Feedback Topologies for the Design of Low-Sensitivity Active Filters , 1979 .

[15]  M. Tarsia,et al.  Design considerations and implementation of a programmable high-frequency continuous-time filter and variable-gain amplifier in submicrometer CMOS , 1999, IEEE J. Solid State Circuits.

[16]  G. Geelen,et al.  A fast-settling CMOS op amp for SC circuits with 90-dB DC gain , 1990 .

[17]  Martin H. Graham,et al.  Book Review: High-Speed Digital Design: A Handbook of Black Magic by Howard W. Johnson and Martin Graham: (Prentice-Hall, 1993) , 1993, CARN.

[18]  Fuji Yang,et al.  A low-distortion BiCMOS seventh-order Bessel filter operating at 2.5 V supply , 1996 .

[19]  Ho-Jun Song,et al.  An MOS four-quadrant analog multiplier using simple two-input squaring circuits with source followers , 1990 .

[20]  A. Boni,et al.  LVDS I/O interface for Gb/s-per-pin operation in 0.35-/spl mu/m CMOS , 2001 .

[21]  Takashi Morie,et al.  A 200-MHz seventh-order equiripple continuous-time filter by design of nonlinearity suppression in 0.25-/spl mu/m CMOS process , 2002 .

[22]  Leonard T. Bruton RC-Active Circuits. Theory and Design , 1980 .

[23]  C. Dualibe,et al.  A linearly tunable low-voltage CMOS transconductor with improved common-mode stability and its application to g/sub m/-C filters , 2001 .

[24]  José Silva-Martínez,et al.  A 150 MHz continuous-time seventh order 0.05/spl deg/ equiripple linear phase filter with automatic tuning system , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[25]  P. Brackett,et al.  Direct SFG simulation of LC ladder networks with applications to active filter design , 1976 .

[26]  Andreas G. Andreou,et al.  Low-voltage/low-power integrated circuits and systems : low-voltage mixed-signal circuits , 1999 .

[27]  Ahmed Nader Mohieldin High performance continuous-time filters for information transfer systems , 2004 .

[28]  Anatol I. Zverev,et al.  Handbook of Filter Synthesis , 1967 .

[29]  Tetsuro Itakura,et al.  A 2 V/sub pp/ linear input-range fully balanced CMOS transconductor and its application to a 2.5 V 2.5 MHz Gm-C LPF , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

[30]  N. Rao,et al.  A 3V 10-100 MHz continuous-time seventh-order 0.05/spl deg/ equiripple linear-phase filter , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[31]  R. Castello,et al.  A 3V 12-55MHz BiCMOS Continuous-Time Filter with Pseudo-Differential Structure , 1995, ESSCIRC '95: Twenty-first European Solid-State Circuits Conference.

[32]  Tawee Tanbun-Ek,et al.  A systems perspective on digital interconnection technology , 1992 .

[33]  J. L. Pennock CMOS triode transconductor for continuous-time active integrated filters , 1985 .

[34]  P. M. Chau,et al.  A 622 MHz stand-alone LVDS driver pad in 0.18-/spl mu/m CMOS , 2001, Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257).