Timing Control Circuit Design for Dual Sampling CMOS Image Sensor

Dual Sampling can be implemented with simple analog circuits to achieve higher dynamic range of CMOS image sensor. Based on the analysis of the principal dual integration and dual sampling with column-level sampling and holding circuits, which can be implement with the same pixel and only small extra processing circuit as to system without dual sampling, a high efficient timing control method is presented. Timing distribution between long integration, short integration and signal processing is optimized in the timing control algorithm, and high frame rate can be achieved. The algorithm implemented with synthesizable verilog code, and the results is successfully tested with function simulation and FPGA verification.