A 3.2-to-4.6 GHz fast-settling all-digital PLL with feed forward frequency presetting

This paper presents a 3.2-to-4.6GHz fast-settling all digital fractional-N phase-locked loop (ADPLL) for multimode multiband receivers. Firstly, in this ADPLL, the wideband digitally controlled oscillator (DCO) is designed with a constant frequency step in the Coarse Mode to ensure constant loop bandwidth in the whole frequency range. Secondly, a feedforward presetting path between frequency command word (FCW) and oscillator tuning word in the Coarse Mode (OTWC) is utilized to accelerate the locking process for large frequency hopping steps. Thirdly, an adaptive locked and unlocked controller (ALUC) is used to allow frequency mode (Coarse/Medium/Fine Mode) to shift automatically. Implemented in a 65 nm CMOS process, the ADPLL on-chip part consumes 16mW at 1V voltage supply. The phase noise at 3.982GHz is −121.8 dBc/Hz@1MHz. The ADPLL with a final bandwidth of 65 kHz exhibits 55 μs transient settling time for a 1.232GHz frequency hopping.

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