Custom implementation of the coarse-grained reconfigurable ADRES architecture for multimedia purposes

Portable wireless multimedia approaches traditionally achieve the specified performance and power consumption with a hardwired accelerator implementation. Due to the increase of algorithm complexity (Shannon's law), flexibility is needed to achieve shorter development cycles. A coarse-grained reconfigurable computing concept for these requirements is discussed, which supports both flexible control decisions and repetitive numerical operations. The concept includes an architecture template and a compiler and simulator environment. The architecture provides flexible time-multiplexing of code for high-performance data processing while keeping the configuration bandwidth and power requirements low. The purpose of this study is to use the coarse-grained architecture for H264/AVC in order to determine at the physical level whether reconfigurable computing, high-performance and low-power can be obtained.

[1]  Ajay Luthra,et al.  Overview of the H.264/AVC video coding standard , 2003, IEEE Trans. Circuits Syst. Video Technol..

[2]  Veredas-Ramirez F-J,et al.  A Survey on Reconfigurable Computing Systems : Taxonomy and Metrics , 2004 .

[3]  Reiner W. Hartenstein,et al.  Coarse grain reconfigurable architecture (embedded tutorial) , 2001, ASP-DAC '01.

[4]  Rudy Lauwereins,et al.  Design methodology for a tightly coupled VLIW/reconfigurable matrix architecture: a case study , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[5]  Gary J. Sullivan,et al.  Rate-constrained coder control and comparison of video coding standards , 2003, IEEE Trans. Circuits Syst. Video Technol..

[6]  Fadi J. Kurdahi,et al.  MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications , 2000, IEEE Trans. Computers.

[7]  P. Groves,et al.  A 600 MHz VLIW DSP , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[8]  Carl Ebeling,et al.  Implementing an OFDM receiver on the RaPiD reconfigurable architecture , 2003, IEEE Transactions on Computers.

[9]  Reiner W. Hartenstein.  Coarse grain reconfigurable architectures , 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).

[10]  Seth Copen Goldstein,et al.  PipeRench: a co/processor for streaming multimedia acceleration , 1999, ISCA.

[11]  Scott Hauck,et al.  The Chimaera reconfigurable functional unit , 1997, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.