Novel probability flipping method for ising annealing chip using circuit unreliability

Abstract Ising chip based on uncertain behaviors of integrated circuits has been introduced to accelerate solving combinatorial optimization problem. However, the way to induce memory error by reducing supply voltage may also cause memory cells that represent interaction coefficients error, which will damage the original problem and obtain incorrect solution. This paper proposes a novel probability flipping method to realize Ising annealing chip by using circuit unreliability. It stores spins in 8-T SRAM and adjusts cell ratio to make it susceptible to circuit noise. Memory error is intentionally induced by reading the cell with high pre-charge bitline voltage and read upset rate can be controlled by the value of pre-charge voltage. The novel approach only probabilistically flips spins in the annealing process but have no influence on the interaction coefficients. Results show that circuit unreliability can be used to escape from local optimum for Ising annealing chip and improve computational performance.