Noise Optimization Techniques for Switched-Capacitor Based Neural Interfaces

This paper presents the noise optimization of a novel switched-capacitor (SC) based neural interface architecture, and its circuit demonstration in a 0.13 <inline-formula><tex-math notation="LaTeX">$\mu\text{m}$</tex-math></inline-formula> CMOS process. To reduce thermal noise folding ratio, and suppress <inline-formula><tex-math notation="LaTeX">$kT/C$</tex-math></inline-formula> noise, several noise optimization techniques are developed in the proposed architecture. First, one parasitic capacitance suppression scheme is developed to block noise charge transfer from parasitic capacitors to amplifier output. Second, one recording path-splitting scheme is proposed in the input sampling stage to selectively record local field potentials (LFPs), extracellular spikes, or both for reducing input noise floor, and total power consumption. Third, an auto-zero noise cancellation scheme is developed to suppress <inline-formula><tex-math notation="LaTeX">$kT/C$</tex-math></inline-formula> noise in the neural amplifier stage. A prototype neural interface chip was fabricated, and also verified in both bench-top, and <italic>In-Vivo</italic> experiments. Bench-top testings show the input-referred noise of the designed chip is 4.8 <inline-formula><tex-math notation="LaTeX">$\mu\text{V}$</tex-math></inline-formula> from 1 <inline-formula><tex-math notation="LaTeX">$\text{Hz}$</tex-math></inline-formula> to 300 <inline-formula><tex-math notation="LaTeX">$\text{Hz}$</tex-math></inline-formula>, and 2.3 <inline-formula><tex-math notation="LaTeX">$\mu\text{V}$</tex-math></inline-formula> from 300 <inline-formula><tex-math notation="LaTeX">$\text{Hz}$</tex-math></inline-formula> to 8 <inline-formula><tex-math notation="LaTeX">$kHz$</tex-math></inline-formula> respectively, and <italic>In-Vivo</italic> experiments show the peak-to-peak amplitude of the total noise floor including neural activity, electrode interface noise, and the designed chip is only around 20 <inline-formula><tex-math notation="LaTeX">$\mu\text{V}$</tex-math></inline-formula>. In comparison with conventional architectures through both circuit measurement and animal experiments, it is well demonstrated that the proposed noise optimization techniques can effectively reduce circuit noise floor, thus extending the application range of switched-capacitor circuits.

[1]  Jian Xu,et al.  A 50 μW/Ch artifacts-insensitive neural recorder using frequency-shaping technique , 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

[2]  Jian Xu,et al.  Ultra low-FOM high-precision ΔΣ modulators with fully-clocked SO and zero static power quantizers , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[3]  Yong-Bin Kim,et al.  Noise Reduction Technique Through Bandwidth Switching for Switched-Capacitor Amplifier , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[4]  Jian Xu,et al.  A 9µW 88dB DR fully-clocked switched-opamp ΔΣ modulator with novel power and area efficient resonator , 2010, IEEE Custom Integrated Circuits Conference 2010.

[5]  Hanqing Wang,et al.  5.7 A 19nV/√Hz-noise 2µV-offset 75µA low-drift capacitive-gain amplifier with switched-capacitor ADC driving capability , 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

[6]  Cl.-A. Gobet,et al.  Noise analysis of switched capacitor networks , 1983 .

[7]  H.C. Luong,et al.  A 28-MHz wideband switched-capacitor bandpass filter with transmission zeros for high attenuation , 2005, IEEE Journal of Solid-State Circuits.

[8]  Bibhudatta Sahoo,et al.  Thermal-Noise-Canceling Switched-Capacitor Circuit , 2016, IEEE Transactions on Circuits and Systems II: Express Briefs.

[9]  Gabor C. Temes,et al.  Correction to "An 8.1 mW, 82 dB Delta-Sigma ADC With 1.9 MHz BW and - 98 dB THD" [Aug 09 2202-2211] , 2010, IEEE J. Solid State Circuits.

[10]  Jian Xu,et al.  A High Performance Delta-Sigma Modulator for Neurosensing , 2015, Sensors.

[11]  Soon-Jyh Chang,et al.  A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure , 2010, IEEE Journal of Solid-State Circuits.

[12]  Maysam Ghovanloo,et al.  An Inductively-Powered Wireless Neural Recording and Stimulation System for Freely-Behaving Animals , 2019, IEEE Transactions on Biomedical Circuits and Systems.

[13]  K. Lee.  Low-destortion switched-capacitor filter design techniques , 1985 .

[14]  Jihyun Cho,et al.  Dynamic Power Reduction in Scalable Neural Recording Interface Using Spatiotemporal Correlation and Temporal Sparsity of Neural Signals , 2018, IEEE Journal of Solid-State Circuits.

[15]  Masanori Furuta,et al.  A 10-bit, 40-MS/s, 1.21 mW Pipelined SAR ADC Using Single-Ended 1.5-bit/cycle Conversion Technique , 2011, IEEE Journal of Solid-State Circuits.

[16]  Jae-Yoon Sim,et al.  A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface , 2011, IEEE Journal of Solid-State Circuits.

[17]  Jordi Parramon,et al.  A Low-Power Configurable Neural Recording System for Epileptic Seizure Detection , 2013, IEEE Transactions on Biomedical Circuits and Systems.

[18]  Un-Ku Moon,et al.  Design of a low-distortion 22-kHz fifth-order Bessel filter , 1993 .

[19]  Robert Bogdan Staszewski,et al.  Analysis and Design of a High-Order Discrete-Time Passive IIR Low-Pass Filter , 2014, IEEE Journal of Solid-State Circuits.

[20]  Jian Xu,et al.  A New System Architecture for Future Long-Term High-Density Neural Recording , 2013, IEEE Transactions on Circuits and Systems II: Express Briefs.

[21]  Daryl R. Kipke,et al.  A Tunable Biquad Switched-Capacitor Amplifier-Filter for Neural Recording , 2010, IEEE Transactions on Biomedical Circuits and Systems.

[22]  Jian Xu,et al.  A Frequency Shaping Neural Recorder With 3 pF Input Capacitance and 11 Plus 4.5 Bits Dynamic Range , 2014, IEEE Transactions on Biomedical Circuits and Systems.

[23]  Karim Abdelhalim,et al.  915-MHz FSK/OOK Wireless Neural Recording SoC With 64 Mixed-Signal FIR Filters , 2013, IEEE Journal of Solid-State Circuits.

[24]  Wenfeng Zhao,et al.  A Low-Noise, Wireless, Frequency-Shaping Neural Recorder , 2018, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[25]  Jun Cheng,et al.  A switched-capacitor programmable-gain amplifier for high-definition video analog front-ends , 2012, 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology.

[26]  R.R. Harrison,et al.  A Low-Power Integrated Circuit for a Wireless 100-Electrode Neural Recording System , 2006, IEEE Journal of Solid-State Circuits.

[27]  Nan Sun,et al.  Thermal Noise Analysis of a Programmable-Gain Switched-Capacitor Amplifier With Input Offset Cancellation , 2013, IEEE Transactions on Circuits and Systems II: Express Briefs.

[28]  H. Ogawa,et al.  A low-power switched-capacitor variable gain amplifier , 2004, IEEE Journal of Solid-State Circuits.

[29]  Gabor C. Temes,et al.  Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization , 1996, Proc. IEEE.