High-Speed Comparator Design for RF-to-Digital Receivers
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Aziza I. Hussein | Ahmed A. Sakr | Ghazal A. Fahmy | Ahmed Sakr | Mahmoud A. Abdelghany | G. Fahmy | A. Hussein | M. Abdelghany
[1] Prashant Dwivedy,et al. Software defined radio based receivers using RTL — SDR: A review , 2017, 2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE).
[2] Eisse Mensink,et al. A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[3] Nuno Borges Carvalho,et al. An Agile and Wideband All-Digital SDR Receiver for 5G Wireless Communications , 2015, 2015 Euromicro Conference on Digital System Design.
[4] Behzad Razavi,et al. RF Microelectronics , 1997 .
[5] Joseph Mitola,et al. The software radio architecture , 1995, IEEE Commun. Mag..
[6] Noriaki Tawa,et al. A 950MHz RF 20MHz bandwidth direct RF sampling bit streamer receiver based on an FPGA , 2017, 2017 IEEE MTT-S International Microwave Symposium (IMS).
[7] Hai Phuong. Le,et al. Performance analysis of optimised CMOS comparator , 2003 .
[8] Horst Zimmermann,et al. A Comparator With Reduced Delay Time in 65-nm CMOS for Supply Voltages Down to 0.65 V , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.
[9] Ashoke Ravi,et al. A Dual-Mode Configurable RF-to-Digital Receiver in 16NM FinFET , 2018, 2018 IEEE Symposium on VLSI Circuits.