The Design and FPGA Implementation of FSM-based Intellectual Property Watermark Algorithm at Behavioral Level

[1]  Miodrag Potkonjak,et al.  Fingerprinting techniques for field-programmable gate arrayintellectual property protection , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Ran Tao,et al.  A Comprehensive Analysis of Digital Watermarking , 2006 .

[3]  Jeffrey J. Rodríguez,et al.  A hierarchy of physical design watermarking schemes for intellectual property protection of IC designs , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[4]  Antonio García,et al.  IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Miodrag Potkonjak,et al.  Effective iterative techniques for fingerprinting design IP , 2004, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Sofiène Tahar,et al.  IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Xiang Wu,et al.  Communication of Mobile Rover Based on FPGA, DSP and Wireless Communication , 2008 .

[8]  A W Jinan Fiaidhi,et al.  Towards Developing Watermarking Standards for Collaborative E-learning Systems , 2003 .

[9]  Zhiqiang Gao,et al.  Constraint-based watermarking technique for hard IP core protection in physical layout design level , 2004, Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004..

[10]  Shi Feng,et al.  Serial ALU Simulation with Timing and Signal Constraints , 2006 .

[11]  Gang Qu,et al.  Publicly detectable watermarking for intellectual property authentication in VLSI design , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Miodrag Potkonjak,et al.  Constraint-based watermarking techniques for design IP protection , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..