Is time predictability quantifiable?

Computer architects and researchers in the real-time domain start to investigate processors and architectures optimized for real-time systems. Optimized for real-time systems means time predictable, i.e., architectures where it is possible to statically derive a tight bound of the worst-case execution time. To compare different approaches we would like to quantify time predictability. That means we need to measure time predictability. In this paper we discuss the different approaches for these measurements and conclude that time predictability is practically not quantifiable. We can only compare the worst-case execution time bounds of different architectures.

[1]  Peter P. Puschner Transforming Execution-Time Boundable Code into Temporally Predictable Code , 2002, DIPES.

[2]  David B. Whalley,et al.  Bounding Pipeline and Instruction Cache Performance , 1999, IEEE Trans. Computers.

[3]  Kees G. W. Goossens,et al.  CoMPSoC: A template for composable and predictable multi-processor system on chips , 2009, TODE.

[4]  Edward A. Lee,et al.  A PRET architecture supporting concurrent programs with composable timing properties , 2010, 2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers.

[5]  Paul Lokuciejewski,et al.  A compiler framework for the reduction of worst-case execution times , 2010, Real-Time Systems.

[6]  Martin Schoeberl,et al.  A real-time Java chip-multiprocessor , 2010, TECS.

[7]  Alan Burns,et al.  Writing temporally predictable code , 2002, Proceedings of the Seventh IEEE International Workshop on Object-Oriented Real-Time Dependable Systems. (WORDS 2002).

[8]  Lothar Thiele,et al.  Design for Timing Predictability , 2004, Real-Time Systems.

[9]  Stephen A. Edwards,et al.  Predictable programming on a precision timed architecture , 2008, CASES '08.

[10]  Kees G. W. Goossens,et al.  Aelite: A flit-synchronous Network on Chip with composable and predictable services , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[11]  Neil C. Audsley,et al.  Time-Predictable Out-of-Order Execution for Hard Real-Time Systems , 2010, IEEE Transactions on Computers.

[12]  Martin Schoeberl,et al.  A Statically Scheduled Time-Division-Multiplexed Network-on-Chip for Real-Time Systems , 2012, 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip.

[13]  Martin Schoeberl,et al.  A Time Predictable Instruction Cache for a Java Processor , 2004, OTM Workshops.

[14]  Reinhard Wilhelm,et al.  The influence of processor architecture on the design and the results of WCET tools , 2003, Proceedings of the IEEE.

[15]  Benedikt Huber,et al.  WCET driven design space exploration of an object cache , 2010, JTRES '10.

[16]  Jan Gustafsson,et al.  The Mälardalen WCET Benchmarks: Past, Present And Future , 2010, WCET.

[17]  Kees G. W. Goossens,et al.  Composability and Predictability for Independent Application Development, Verification, and Execution , 2011, Multiprocessor System-on-Chip.

[18]  Jan Reineke,et al.  Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-Critical Embedded Systems , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[19]  Raimund Kirner,et al.  Time-Predictable Computing , 2010, SEUS.

[20]  Jiri Gaisler A portable and fault-tolerant microprocessor based on the SPARC v8 architecture , 2002, Proceedings International Conference on Dependable Systems and Networks.

[21]  Francisco J. Cazorla,et al.  Hardware support for WCET analysis of hard real-time multicore systems , 2009, ISCA '09.

[22]  Heiko Falk,et al.  Optimal static WCET-aware scratchpad allocation of program code , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[23]  Martin Schoeberl,et al.  A Java processor architecture for embedded real-time systems , 2008, J. Syst. Archit..

[24]  Jack Whitham,et al.  Real-time processor architectures for worst case execution time reduction , 2008 .

[25]  Sascha Uhrig,et al.  Predictable dynamic instruction scratchpad for simultaneous multithreaded processors , 2008, MEDEA '08.

[26]  Stephen A. Edwards,et al.  The Case for the Precision Timed (PRET) Machine , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[27]  Jakob Engblom,et al.  Requirements for and Design of a Processor with Predictable Timing , 2004, Design of Systems with Predictable Behaviour.

[28]  Martin Schoeberl,et al.  Time-predictable Cache Organization , 2009, 2009 Software Technologies for Future Dependable Distributed Systems.

[29]  Kees G. W. Goossens,et al.  Predator: A predictable SDRAM memory controller , 2007, 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[30]  Stephen A. Edwards,et al.  A disruptive computer design idea: Architectures with repeatable timing , 2009, 2009 IEEE International Conference on Computer Design.

[31]  David B. Whalley,et al.  Bounding worst-case instruction cache performance , 1994, 1994 Proceedings Real-Time Systems Symposium.

[32]  Neil C. Audsley,et al.  Using Trace Scratchpads to Reduce Execution Times in Predictable Real-Time Architectures , 2008, 2008 IEEE Real-Time and Embedded Technology and Applications Symposium.

[33]  Martin Schoeberl,et al.  Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach , 2011, PPES.

[34]  Gerard J. M. Smit,et al.  A mathematical approach towards hardware design , 2010, Dynamically Reconfigurable Architectures.

[35]  Jan Reineke,et al.  A Template for Predictability Definitions with Supporting Evidence , 2011, PPES.