Specification of interface components for synchronous data paths

The simulation semantics of VHDL necessitates the specification of the interface signal transitions at bit level with exact timing which is not well suited for abstract specification and synthesis. The paper shows a methodology to model the interface of a behavioural description suited for high level synthesis where different abstraction levels are separated. It shows the transformations to generate a RT data path while holding the exact simulation semantics at the interface.<<ETX>>

[1]  Wayne Wolf,et al.  Modular scheduling constraint specification , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

[2]  Wolfgang Rosenstiel,et al.  Interface specification and synthesis for VHDL processes , 1993, Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference.

[3]  Raul Camposano,et al.  VHDL as input for high-level synthesis , 1991, IEEE Design & Test of Computers.

[4]  Gaetano Borriello.  Combining event and data-flow graphs in behavioral synthesis , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[5]  Peter Duzy,et al.  High-level synthesis from VHDL with exact timing constraints , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[6]  Carlo H. Séquin,et al.  OPERATION/EVENT GRAPHS: A Design Representation for Timing Behavior , 1991 .