Correlations between CMOS latch-up characteristics and substrate structure parameters

Abstract A structure-oriented model based on a simplified two-dimensional numerical analysis has been developed to calculate the substrate spreading resistance of a parasitic SCR latch-up path in a CMOS circuit. This model establishes the correlation between the major latch-up characteristics parameters (holding voltage, holding current and triggering current) and the structure parameters in the substrate. The correlations thus obtained have been used to predict the effects of layout and structural changes in the substrate on the latch-up characteristics through the application of this model. It has been verified that the calculated results are in good agreement with both the experimental results of the fabricated devices and the simulation results based on the exact two-dimensional numerical analysis.