Fully packaged 11 Gb/s parallel processing decision circuit using sub-micron silicon bipolar ICs
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[1] K. Runge,et al. Submicron silicon bipolar master-slave D-type flip-flop for use as 8.1 Gbit/s decision circuit and 11.2 Gbit/s demultiplexer , 1989 .
[2] D. Clawin,et al. Multigigabit/second silicon decision circuit , 1985, 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[3] H. Ichino,et al. A bipolar monolithic multigigabit/s decision circuit , 1984, IEEE Journal of Solid-State Circuits.
[4] W. S. Holden,et al. 11.4 Gb/s multiplexer for future broadband communications networks , 1989, Proceedings of the Bipolar Circuits and Technology Meeting.