Verification techniques for cache coherence protocols

In this article we present a comprehensive survey of various approaches for the verification of cache coherence protocols based on state enumeration, (symbolic model checking, and symbolic state models. Since these techniques search the state space of the protocol exhaustively, the amount of memory required to manipulate that state information and the verification time grow very fast with the number of processors and the complexity of the protocol mechanisms. To be successful for systems of arbitrary complexity, a verification technique must solve this so-called state space explosion problem. The emphasis of our discussion is onthe underlying theory in each method of handling the state space exposion problem, and formulationg and checking the safety properties (e.g., data consistency) and the liveness properties (absence of deadlock and livelock). We compare the efficiency and discuss the limitations of each technique in terms of memory and computation time. Also, we discuss issues of generality, applicability, automaticity, and amenity for existing tools in each class of methods. No method is truly superior because each method has its own strengths and weaknesses. Finally, refinements that can further reduce the verification time and/or the memory requirement are also discussed.

[1]  Thierry Jéron,et al.  Bounded-memory Algorithms for Verification On-the-fly , 1991, CAV.

[2]  Edmund M. Clarke,et al.  Automatic Verification of Sequential Circuits Using Temporal Logic , 1986, IEEE Transactions on Computers.

[3]  David L. Dill,et al.  Verification of a Multiprocessor Cache Protocol Using Simulation Relations and Higher-Order Logic , 1990, CAV.

[4]  Laxmi N. Bhuyan,et al.  A Formal Specification and Verification Technique for Cache Coherence Protocols , 1992, ICPP.

[5]  J. K. Archibald.  The cache coherence problem in shared-memory multiprocessors , 1987 .

[6]  Amir Pnueli.  The Temporal Semantics of Concurrent Programs , 1981, Theor. Comput. Sci..

[7]  Albert R. Wang,et al.  Logic verification using binary decision diagrams in a logic synthesis environment , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[8]  William W. Collier,et al.  Reasoning about parallel architectures , 1992 .

[9]  David L. Dill,et al.  Better verification through symmetry , 1996, Formal Methods Syst. Des..

[10]  J. Kubiatowicz.  Closing the Window of Vulnerability in Multiphase memory transaction: The alewife transaction store , 1993 .

[11]  David L. Dill,et al.  Efficient verification of symmetric concurrent systems , 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

[12]  Robert K. Brayton,et al.  Automatic compositional minimization in CTL model checking , 1992, ICCAD.

[13]  M.C. Yuang,et al.  Survey of protocol verification techniques based on finite state machine models , 1988, [1988] Proceedings. Computer Networking Symposium.

[14]  Michel Dubois,et al.  Formal verification of delayed consistency protocols , 1996, Proceedings of International Conference on Parallel Processing.

[15]  Thomas Filkorn,et al.  Generating BDDs for Symbolic Model Checking in CCS , 1991, CAV.

[16]  Keshab K. Parhi,et al.  Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors , 1999 .

[17]  Robert P. Kurshan,et al.  A structural induction theorem for processes , 1989, PODC.

[18]  Kourosh Gharachorloo,et al.  Proving sequential consistency of high-performance shared memories (extended abstract) , 1991, SPAA '91.

[19]  Michel Dubois,et al.  Combined performance gains of simple cache protocol extensions , 1994, ISCA '94.

[20]  Masahiro Fujita,et al.  Evaluation and improvement of Boolean comparison method based on binary decision diagrams , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[21]  Michel Dubois,et al.  Lockup-free Caches in High-Performance Multiprocessors , 1990, J. Parallel Distributed Comput..

[22]  A. Danthine,et al.  Protocol Representation with Finite-State Models , 1980, IEEE Trans. Commun..

[23]  Claire Loiseaux,et al.  A Tool for Symbolic Program Verification and Abstration , 1993, CAV.

[24]  Patrice Godefroid.  Using Partial Orders to Improve Automatic Verification Methods , 1990, CAV.

[25]  藤田 昌宏,et al.  Evaluation and Improvements of Boolean Comparison Method Based on Binary Decision Diagrams , 1988 .

[26]  Chen-Shang Lin,et al.  On the OBDD-Representation of General Boolean Functions , 1992, IEEE Trans. Computers.

[27]  Anoop Gupta,et al.  The directory-based cache coherence protocol for the DASH multiprocessor , 1990, ISCA '90.

[28]  Michael C. Browne,et al.  The S3.mp scalable shared memory multiprocessor , 1994, 1994 Proceedings of the Twenty-Seventh Hawaii International Conference on System Sciences.

[29]  Kenneth J. Supowit,et al.  Finding the Optimal Variable Ordering for Binary Decision Diagrams , 1987, 24th ACM/IEEE Design Automation Conference.

[30]  Martin Peschke,et al.  Design and Validation of Computer Protocols , 2003 .

[31]  Pierre Wolper,et al.  Reliable Hashing without Collosion Detection , 1993, CAV.

[32]  Somesh Jha,et al.  Exploiting Symmetry In Temporal Logic Model Checking , 1993, CAV.

[33]  Michel Dubois,et al.  Memory access buffering in multiprocessors , 1998, ISCA '98.

[34]  Somesh Jha,et al.  Exploiting symmetry in temporal logic model checking , 1993, Formal Methods Syst. Des..

[35]  Robert K. Brayton,et al.  Automatic Reduction in CTL Compositional Model Checking , 1992, CAV.

[36]  Carlos Rodriguez,et al.  What are the Limits of Model Checking Methods for the Verification of Real Life Protocols? , 1989, Automatic Verification Methods for Finite State Systems.

[37]  Paul Feautrier,et al.  A New Solution to Coherence Problems in Multicache Systems , 1978, IEEE Transactions on Computers.

[38]  Michel Dubois,et al.  A New Approach for the Verification of Cache Coherence Protocols , 1995, IEEE Trans. Parallel Distributed Syst..

[39]  Eric Williams,et al.  Performance optimizations, implementation, and verification of the SGI Challenge multiprocessor , 1994, 1994 Proceedings of the Twenty-Seventh Hawaii International Conference on System Sciences.

[40]  Alan J. Hu,et al.  Higher-Level Specification and Verification with BDDs , 1992, CAV.

[41]  Michel Dubois,et al.  Delayed consistency and its effects on the miss rate of parallel programs , 1991, Proceedings of the 1991 ACM/IEEE Conference on Supercomputing (Supercomputing '91).

[42]  Stein Gjessing,et al.  Distributed-directory scheme: scalable coherent interface , 1990, Computer.

[43]  Michel Dubois,et al.  Memory Access Dependencies in Shared-Memory Multiprocessors , 1990, IEEE Trans. Software Eng..

[44]  King-Sun Fu,et al.  Data Coherence Problem in a Multicache System , 1985, IEEE Transactions on Computers.

[45]  A. Prasad Sistla,et al.  Symmetry and model checking , 1993, Formal Methods Syst. Des..

[46]  Leslie Lamport,et al.  How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs , 2016, IEEE Transactions on Computers.

[47]  Michel Dubois,et al.  The verification of cache coherence protocols , 1993, SPAA '93.

[48]  Gerard J. Holzmann,et al.  State-space caching revisited , 1992, Formal Methods Syst. Des..

[49]  Donald E. Thomas,et al.  The Verilog hardware description language (4th ed.) , 1998 .

[50]  Erik Hagersten,et al.  The Cache Coherence Protocol of the Data Diffusion Machine , 1989 .

[51]  Alan Jay Smith,et al.  A class of compatible cache consistency protocols and their support by the IEEE futurebus , 1986, ISCA '86.

[52]  James K. Archibald,et al.  Cache coherence protocols: evaluation using a multiprocessor simulation model , 1986, TOCS.

[53]  Susanne Graf,et al.  Verification of a Distributed Cache Memory by Using Abstractions , 1994, CAV.

[54]  Yehuda Afek,et al.  A lazy cache algorithm , 1989, SPAA '89.

[55]  Alan Jay Smith,et al.  A class of compatible cache consistency protocols and their support by the IEEE futurebus , 1986, ISCA '86.

[56]  Alan J. Hu,et al.  Reducing BDD Size by Exploiting Functional Dependencies , 1993, 30th ACM/IEEE Design Automation Conference.

[57]  Alan J. Hu,et al.  Efficient Verification with BDDs using Implicitly Conjoined Invariants , 1993, CAV.

[58]  Michel Cekleov,et al.  Formal Specification of Memory Models , 1992 .

[59]  Michel Dubois,et al.  An Integrated Methodology for the Verification of Directory-Based Cache Protocols , 1994, 1994 International Conference on Parallel Processing Vol. 1.

[60]  Michel Dubois,et al.  Correctness of a directory-based cache coherence protocol: Early experience , 1993, Proceedings of 1993 5th IEEE Symposium on Parallel and Distributed Processing.

[61]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[62]  Jean Christophe Madre,et al.  Proving circuit correctness using formal comparison between expected and extracted behaviour , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[63]  Edmund M. Clarke,et al.  Reasoning about networks with many identical finite-state processes , 1986, PODC '86.

[64]  Larry Rudolph,et al.  Dynamic decentralized cache schemes for mimd parallel processors , 1984, ISCA 1984.

[65]  共立出版株式会社.  コンピュータ・サイエンス : ACM computing surveys , 1978 .

[66]  G. J. Holzmann,et al.  Tracing protocols , 1985, AT&T Technical Journal.

[67]  Anoop Gupta,et al.  Memory consistency and event ordering in scalable shared-memory multiprocessors , 1990, ISCA '90.

[68]  Donald E. Thomas,et al.  The Verilog® Hardware Description Language , 1990 .

[69]  Michel Dubois,et al.  RPM: A Rapid Prototyping Engine for Multiprocessor Systems , 1995, Computer.

[70]  ShashaDennis,et al.  Efficient and correct execution of parallel programs that share memory , 1988 .

[71]  Ingo Wegener.  The Size of Reduced OBDDs and Optimal Read-once Branching Programs for Almost all Boolean Functions , 1993, WG.

[72]  Mark D. Hill,et al.  A Unified Formalization of Four Shared-Memory Models , 1993, IEEE Trans. Parallel Distributed Syst..

[73]  Pierre Wolper,et al.  Verifying Properties of Large Sets of Processes with Network Invariants , 1990, Automatic Verification Methods for Finite State Systems.

[74]  Michel Dubois,et al.  Verifying Distributed Directory-Based Cahce Coherence Protocols: S3.mp, a Case Study , 1995, Euro-Par.

[75]  Anant Agarwal,et al.  Closing the window of vulnerability in multiphase memory transactions , 1992, ASPLOS V.

[76]  Michel Dubois,et al.  Access ordering and coherence in shared memory multiprocessors , 1989 .

[77]  Olivier Coudert,et al.  Verifying Temporal Properties of Sequential Machines without Building Their State Diagrams , 1990, CAV.

[78]  Alan J. Hu,et al.  Protocol verification as a hardware design aid , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[79]  Per Stenström,et al.  A Survey of Cache Coherence Schemes for Multiprocessors , 1990, Computer.

[80]  Somesh Jha,et al.  Verification of the Futurebus+ cache coherence protocol , 1993, Formal Methods Syst. Des..

[81]  Fred Kröger,et al.  Temporal Logic of Programs , 1987, EATCS Monographs on Theoretical Computer Science.

[82]  Olivier Coudert,et al.  Verification of Synchronous Sequential Machines Based on Symbolic Execution , 1989, Automatic Verification Methods for Finite State Systems.

[83]  Anoop Gupta,et al.  Comparative evaluation of latency reducing and tolerating techniques , 1991, ISCA '91.

[84]  Patrick Cousot,et al.  Abstract Interpretation Frameworks , 1992, J. Log. Comput..

[85]  Ingo Wegener.  The Size of Reduced OBDD's and Optimal Read-Once Branching Programs for Almost All Boolean Functions , 1994, IEEE Trans. Computers.

[86]  Joseph Sifakis,et al.  Automatic Verification Methods for Finite State Systems , 1989, Lecture Notes in Computer Science.

[87]  Erik Hagersten,et al.  The Cache Coherence Protocol of the Data Diffusion Machine , 1989, PARLE.

[88]  Kenneth L. McMillan,et al.  Symbolic model checking: an approach to the state explosion problem , 1992 .

[89]  M. Hill,et al.  Weak ordering-a new definition , 1990, [1990] Proceedings. The 17th Annual International Symposium on Computer Architecture.

[90]  R. Brayton,et al.  Automatic compositional minimization in CTL model checking , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[91]  Geoffrey M. Brown.  Asynchronous multicaches , 1990, Distributed Computing.

[92]  Edmund M. Clarke,et al.  Symbolic Model Checking with Partitioned Transistion Relations , 1991, VLSI.

[93]  Gregor von Bochmann,et al.  Formal Methods in Communication Protocol Design , 1980, IEEE Trans. Commun..

[94]  Gerard J. Holzmann.  Algorithms for automated protocol verification , 1990, AT&T Technical Journal.

[95]  Anoop Gupta,et al.  Performance evaluation of memory consistency models for shared-memory multiprocessors , 1991, ASPLOS IV.

[96]  Pong Fong.  Symbolic state model: a new approach for the verification of cache coherence protocols , 1996 .

[97]  Andrew W. Wilson,et al.  Hierarchical cache/bus architecture for shared memory multiprocessors , 1987, ISCA '87.

[98]  P. Stenstrom.  A survey of cache coherence schemes for multiprocessors , 1990, Computer.

[99]  C. A. R. Hoare,et al.  Communicating sequential processes , 1978, CACM.

[100]  Mark D. Hill,et al.  Weak ordering—a new definition , 1998, ISCA '98.

[101]  Amir Pnueli,et al.  The temporal logic of programs , 1977, 18th Annual Symposium on Foundations of Computer Science (sfcs 1977).

[102]  Michel Dubois,et al.  Correct memory operation of cache-based multiprocessors , 1987, ISCA '87.

[103]  Larry Rudolph,et al.  Dynamic decentralized cache schemes for mimd parallel processors , 1984, ISCA '84.

[104]  DuboisMichel,et al.  Verification techniques for cache coherence protocols , 1997 .

[105]  Dennis Shasha,et al.  Efficient and correct execution of parallel programs that share memory , 1988, TOPL.

[106]  Mark D. Hill,et al.  Implementing Sequential Consistency in Cache-Based Systems , 1990, ICPP.

[107]  Stein Gjessing,et al.  A Top Down Approach to the Formal Specification of SCI Cache Coherence , 1991, CAV.

[108]  Randal E. Bryant,et al.  Symbolic Boolean manipulation with ordered binary-decision diagrams , 1992, CSUR.